changeset 5e3367b103da in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5e3367b103da
description:
X86: Do a merge for the zero extension microop.
diffstat:
7 files changed, 17 insertions(+), 17 deletions(-)
src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py | 2
+-
src/arch/x86/isa/insts/general_purpose/data_transfer/move.py | 6
+++---
src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py | 4
++--
src/arch/x86/isa/insts/general_purpose/input_output/general_io.py | 4
++--
src/arch/x86/isa/insts/general_purpose/input_output/string_io.py | 8
++++----
src/arch/x86/isa/insts/system/segmentation.py | 8
++++----
src/arch/x86/isa/microops/regop.isa | 2
+-
diffs (168 lines):
diff -r c182698e1ab3 -r 5e3367b103da
src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py
--- a/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py
Wed Feb 25 10:20:01 2009 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py
Wed Feb 25 10:20:10 2009 -0800
@@ -55,7 +55,7 @@
microcode = '''
def macroop XLAT {
- zexti t1, rax, 7
+ zexti t1, rax, 7, dataSize=8
# Here, t1 can be used directly. The value of al is supposed to be treated
# as unsigned. Since we zero extended it from 8 bits above and the address
# size has to be at least 16 bits, t1 will not be sign extended.
diff -r c182698e1ab3 -r 5e3367b103da
src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py Wed Feb
25 10:20:01 2009 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py Wed Feb
25 10:20:10 2009 -0800
@@ -215,7 +215,7 @@
};
def macroop MOV_REAL_S_R {
- zext t2, regm, 15
+ zext t2, regm, 15, dataSize=8
slli t3, t2, 2, dataSize=8
wrsel reg, regm
wrbase reg, t3
@@ -223,7 +223,7 @@
def macroop MOV_REAL_S_M {
ld t1, seg, sib, disp, dataSize=2
- zext t2, t1, 15
+ zext t2, t1, 15, dataSize=8
slli t3, t2, 2, dataSize=8
wrsel reg, t1
wrbase reg, t3
@@ -232,7 +232,7 @@
def macroop MOV_REAL_S_P {
rdip t7
ld t1, seg, riprel, disp, dataSize=2
- zext t2, t1, 15
+ zext t2, t1, 15, dataSize=8
slli t3, t2, 2, dataSize=8
wrsel reg, t1
wrbase reg, t3
diff -r c182698e1ab3 -r 5e3367b103da
src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
Wed Feb 25 10:20:01 2009 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
Wed Feb 25 10:20:10 2009 -0800
@@ -162,9 +162,9 @@
# Pull the different components out of the immediate
limm t1, imm
- zexti t2, t1, 15, dataSize=2
+ zexti t2, t1, 15, dataSize=8
srl t1, t1, 16
- zexti t1, t1, 5
+ zexti t1, t1, 5, dataSize=8
# t1 is now the masked nesting level, and t2 is the amount of storage.
# Push rbp.
diff -r c182698e1ab3 -r 5e3367b103da
src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
--- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py Wed Feb
25 10:20:01 2009 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py Wed Feb
25 10:20:10 2009 -0800
@@ -89,7 +89,7 @@
};
def macroop IN_R_R {
- zexti t2, regm, 15, dataSize=2
+ zexti t2, regm, 15, dataSize=8
ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
};
@@ -100,7 +100,7 @@
};
def macroop OUT_R_R {
- zexti t2, reg, 15, dataSize=2
+ zexti t2, reg, 15, dataSize=8
st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
};
'''
diff -r c182698e1ab3 -r 5e3367b103da
src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
--- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py Wed Feb
25 10:20:01 2009 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py Wed Feb
25 10:20:10 2009 -0800
@@ -61,7 +61,7 @@
subi t4, t0, dsz, dataSize=asz
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
- zexti t2, reg, 15, dataSize=2
+ zexti t2, reg, 15, dataSize=8
ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
st t6, es, [1, t0, rdi]
@@ -78,7 +78,7 @@
subi t4, t0, dsz, dataSize=asz
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
- zexti t2, reg, 15, dataSize=2
+ zexti t2, reg, 15, dataSize=8
topOfLoop:
ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
@@ -98,7 +98,7 @@
subi t4, t0, dsz, dataSize=asz
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
- zexti t2, reg, 15, dataSize=2
+ zexti t2, reg, 15, dataSize=8
ld t6, ds, [1, t0, rsi]
st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
@@ -115,7 +115,7 @@
subi t4, t0, dsz, dataSize=asz
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
- zexti t2, reg, 15, dataSize=2
+ zexti t2, reg, 15, dataSize=8
topOfLoop:
ld t6, ds, [1, t0, rsi]
diff -r c182698e1ab3 -r 5e3367b103da
src/arch/x86/isa/insts/system/segmentation.py
--- a/src/arch/x86/isa/insts/system/segmentation.py Wed Feb 25 10:20:01
2009 -0800
+++ b/src/arch/x86/isa/insts/system/segmentation.py Wed Feb 25 10:20:10
2009 -0800
@@ -92,7 +92,7 @@
ld t1, seg, sib, disp, dataSize=2
# Get the base
ld t2, seg, sib, 'adjustedDisp + 2', dataSize=4
- zexti t2, t2, 23
+ zexti t2, t2, 23, dataSize=8
wrbase tsg, t2
wrlimit tsg, t1
};
@@ -106,7 +106,7 @@
ld t1, seg, riprel, disp, dataSize=2
# Get the base
ld t2, seg, riprel, 'adjustedDisp + 2', dataSize=4
- zexti t2, t2, 23
+ zexti t2, t2, 23, dataSize=8
wrbase tsg, t2
wrlimit tsg, t1
};
@@ -149,7 +149,7 @@
ld t1, seg, sib, disp, dataSize=2
# Get the base
ld t2, seg, sib, 'adjustedDisp + 2', dataSize=4
- zexti t2, t2, 23
+ zexti t2, t2, 23, dataSize=8
wrbase idtr, t2
wrlimit idtr, t1
};
@@ -163,7 +163,7 @@
ld t1, seg, riprel, disp, dataSize=2
# Get the base
ld t2, seg, riprel, 'adjustedDisp + 2', dataSize=4
- zexti t2, t2, 23
+ zexti t2, t2, 23, dataSize=8
wrbase idtr, t2
wrlimit idtr, t1
};
diff -r c182698e1ab3 -r 5e3367b103da src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Wed Feb 25 10:20:01 2009 -0800
+++ b/src/arch/x86/isa/microops/regop.isa Wed Feb 25 10:20:10 2009 -0800
@@ -921,7 +921,7 @@
'''
class Zext(RegOp):
- code = 'DestReg = bits(psrc1, op2, 0);'
+ code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
class Rddr(RegOp):
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
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