changeset d42d507ccdb1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d42d507ccdb1
description:
X86: Implement the mov to debug register intructions.
diffstat:
2 files changed, 12 insertions(+), 2 deletions(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa | 4 ++--
src/arch/x86/isa/insts/general_purpose/data_transfer/move.py | 10 ++++++++++
diffs (35 lines):
diff -r ec124ac0984b -r d42d507ccdb1
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Wed Feb 25 10:20:30
2009 -0800
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Wed Feb 25 10:20:42
2009 -0800
@@ -352,9 +352,9 @@
// no prefix
0x0: decode OPCODE_OP_BOTTOM3 {
0x0: Inst::MOV(Rd,Cd);
- 0x1: mov_Rd_Dd();
+ 0x1: Inst::MOV(Rd,Dd);
0x2: Inst::MOV(Cd,Rd);
- 0x3: mov_Dd_Rd();
+ 0x3: Inst::MOV(Dd,Rd);
0x4: mov_Rd_Td();
0x6: mov_Td_Rd();
default: Inst::UD2();
diff -r ec124ac0984b -r d42d507ccdb1
src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py Wed Feb
25 10:20:30 2009 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py Wed Feb
25 10:20:42 2009 -0800
@@ -199,6 +199,16 @@
rdcr reg, regm
};
+def macroop MOV_D_R {
+ .adjust_env maxOsz
+ wrdr reg, regm
+};
+
+def macroop MOV_R_D {
+ .adjust_env maxOsz
+ rddr reg, regm
+};
+
def macroop MOV_R_S {
rdsel reg, regm
};
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
