changeset afa0866171e1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=afa0866171e1
description:
X86: Make the segment register reading microops use merge.
diffstat:
2 files changed, 5 insertions(+), 5 deletions(-)
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
| 2 +-
src/arch/x86/isa/microops/regop.isa
| 8 ++++----
diffs (42 lines):
diff -r d42d507ccdb1 -r afa0866171e1
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
---
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
Wed Feb 25 10:20:42 2009 -0800
+++
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
Wed Feb 25 10:20:47 2009 -0800
@@ -142,7 +142,7 @@
# Here, we know we're -not- in 64 bit mode, so we should do the
# appropriate/other RIP checks.
# if temp_RIP > CS.limit throw #GP(0)
- rdlimit t6, cs
+ rdlimit t6, cs, dataSize=8
subi t0, t1, t6, flags=(ECF,)
fault "new GeneralProtection(0)", flags=(CECF,)
diff -r d42d507ccdb1 -r afa0866171e1 src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Wed Feb 25 10:20:42 2009 -0800
+++ b/src/arch/x86/isa/microops/regop.isa Wed Feb 25 10:20:47 2009 -0800
@@ -1052,22 +1052,22 @@
class Rdbase(SegOp):
code = '''
- DestReg = SegBaseSrc1;
+ DestReg = merge(DestReg, SegBaseSrc1, dataSize);
'''
class Rdlimit(SegOp):
code = '''
- DestReg = SegLimitSrc1;
+ DestReg = merge(DestReg, SegLimitSrc1, dataSize);
'''
class RdAttr(SegOp):
code = '''
- DestReg = SegAttrSrc1;
+ DestReg = merge(DestReg, SegAttrSrc1, dataSize);
'''
class Rdsel(SegOp):
code = '''
- DestReg = SegSelSrc1;
+ DestReg = merge(DestReg, SegSelSrc1, dataSize);
'''
class Rdval(RegOp):
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