changeset 367ac7cae7b5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=367ac7cae7b5
description:
X86: Make rdcr use merge and the mov to control register instructions
use the right operand size.
diffstat:
2 files changed, 3 insertions(+), 1 deletion(-)
src/arch/x86/isa/insts/general_purpose/data_transfer/move.py | 2 ++
src/arch/x86/isa/microops/regop.isa | 2 +-
diffs (28 lines):
diff -r 8b9bc09b149c -r 367ac7cae7b5
src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py Wed Feb
25 10:21:02 2009 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py Wed Feb
25 10:21:08 2009 -0800
@@ -192,10 +192,12 @@
};
def macroop MOV_C_R {
+ .adjust_env maxOsz
wrcr reg, regm
};
def macroop MOV_R_C {
+ .adjust_env maxOsz
rdcr reg, regm
};
diff -r 8b9bc09b149c -r 367ac7cae7b5 src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Wed Feb 25 10:21:02 2009 -0800
+++ b/src/arch/x86/isa/microops/regop.isa Wed Feb 25 10:21:08 2009 -0800
@@ -967,7 +967,7 @@
if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
fault = new InvalidOpcode();
} else {
- DestReg = ControlSrc1;
+ DestReg = merge(DestReg, ControlSrc1, dataSize);
}
'''
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