changeset 6f9f1438360a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6f9f1438360a
description:
X86: Make instructions that use intseg preserve all 8 bytes of their
addresses.
diffstat:
2 files changed, 6 insertions(+), 6 deletions(-)
src/arch/x86/isa/insts/general_purpose/input_output/general_io.py | 8
++++----
src/arch/x86/isa/insts/system/msrs.py | 4 ++--
diffs (51 lines):
diff -r ff9203dd7608 -r 6f9f1438360a
src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
--- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py Fri Feb
27 09:24:10 2009 -0800
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py Fri Feb
27 09:25:02 2009 -0800
@@ -85,22 +85,22 @@
def macroop IN_R_I {
.adjust_imm trimImm(8)
limm t1, imm, dataSize=asz
- ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
+ ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8
};
def macroop IN_R_R {
zexti t2, regm, 15, dataSize=8
- ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
+ ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
};
def macroop OUT_I_R {
.adjust_imm trimImm(8)
limm t1, imm, dataSize=8
- st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
+ st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8
};
def macroop OUT_R_R {
zexti t2, reg, 15, dataSize=8
- st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
+ st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
};
'''
diff -r ff9203dd7608 -r 6f9f1438360a src/arch/x86/isa/insts/system/msrs.py
--- a/src/arch/x86/isa/insts/system/msrs.py Fri Feb 27 09:24:10 2009 -0800
+++ b/src/arch/x86/isa/insts/system/msrs.py Fri Feb 27 09:25:02 2009 -0800
@@ -85,7 +85,7 @@
def macroop RDMSR
{
ld t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
- dataSize=8, addressSize=4
+ dataSize=8, addressSize=8
mov rax, rax, t2, dataSize=4
srli t2, t2, 32, dataSize=8
mov rdx, rdx, t2, dataSize=4
@@ -97,7 +97,7 @@
slli t3, rdx, 32, dataSize=8
or t2, t2, t3, dataSize=8
st t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
- dataSize=8, addressSize=4
+ dataSize=8, addressSize=8
};
def macroop RDTSC
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