changeset 0ea37baabfb0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0ea37baabfb0
description:
quell gcc 4.3 warning
diffstat:
1 file changed, 4 insertions(+), 4 deletions(-)
src/arch/x86/tlb.cc | 8 ++++----
diffs (25 lines):
diff -r d4cb6394049b -r 0ea37baabfb0 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Fri Feb 27 09:26:41 2009 -0800
+++ b/src/arch/x86/tlb.cc Fri Feb 27 17:29:58 2009 -0800
@@ -590,8 +590,8 @@
// address size is 64 bits, overridable to 32.
int size = 32;
bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
- if (csAttr.defaultSize && sizeOverride ||
- !csAttr.defaultSize && !sizeOverride)
+ if ((csAttr.defaultSize && sizeOverride) ||
+ (!csAttr.defaultSize && !sizeOverride))
size = 16;
Addr offset = bits(vaddr - base, size-1, 0);
Addr endOffset = offset + req->getSize() - 1;
@@ -647,8 +647,8 @@
// Do paging protection checks.
bool inUser = (csAttr.dpl == 3 &&
!(flags & (CPL0FlagBit << FlagShift)));
- if (inUser && !entry->user ||
- write && !entry->writable) {
+ if ((inUser && !entry->user) ||
+ (write && !entry->writable)) {
// The page must have been present to get into the TLB in
// the first place. We'll assume the reserved bits are
// fine even though we're not checking them.
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