changeset 77bf0b8db2c5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=77bf0b8db2c5
description:
Very minor regression stats updates due top previous changeset.
Setting dirty bit on swaps added a handful of writebacks in a
few of the longer-running SPARC_SE benchmarks.
diffstat:
8 files changed, 266 insertions(+), 266 deletions(-)
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout | 12
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 350 +++++-----
tests/long/00.gzip/ref/sparc/linux/simple-timing/simout | 12
tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt | 96 +-
tests/long/10.mcf/ref/sparc/linux/simple-timing/simout | 10
tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt | 16
tests/long/50.vortex/ref/sparc/linux/simple-timing/simout | 10
tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt | 26
diffs (truncated from 949 to 300 lines):
diff -r 208de84f046d -r 77bf0b8db2c5
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout Wed Mar 11
23:05:26 2009 -0700
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout Mon Mar 16
11:01:23 2009 -0400
@@ -5,11 +5,11 @@
All Rights Reserved
-M5 compiled Mar 6 2009 18:29:06
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar 6 2009 18:38:25
-M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/SPARC_SE/m5.fast -d
/n/blue/z/binkert/build/work/build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
-re tests/run.py long/00.gzip/sparc/linux/o3-timing
+M5 compiled Mar 16 2009 00:51:12
+M5 revision 208de84f046d 6013 default tip
+M5 started Mar 16 2009 00:51:29
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d
build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py
build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@@ -43,4 +43,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 1102659164000 because target called exit()
+Exiting @ tick 1102659088000 because target called exit()
diff -r 208de84f046d -r 77bf0b8db2c5
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt Wed Mar 11
23:05:26 2009 -0700
+++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt Mon Mar 16
11:01:23 2009 -0400
@@ -1,36 +1,36 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 148318 #
Simulator instruction rate (inst/s)
-host_mem_usage 208044 #
Number of bytes of host memory used
-host_seconds 9477.08 #
Real time elapsed on the host
-host_tick_rate 116350072 #
Simulator tick rate (ticks/s)
+host_inst_rate 159348 #
Simulator instruction rate (inst/s)
+host_mem_usage 206344 #
Number of bytes of host memory used
+host_seconds 8821.04 #
Real time elapsed on the host
+host_tick_rate 125003315 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 1405618365 #
Number of instructions simulated
sim_seconds 1.102659 #
Number of seconds simulated
-sim_ticks 1102659164000 #
Number of ticks simulated
+sim_ticks 1102659088000 #
Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 182414509 #
Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 203429504 #
Number of BTB lookups
+system.cpu.BPredUnit.BTBLookups 203429498 #
Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 #
Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 83681535 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 254458067 #
Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 254458067 #
Number of BP lookups
+system.cpu.BPredUnit.condPredicted 254458061 #
Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 254458061 #
Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 #
Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 86248929 #
Number of branches committed
-system.cpu.commit.COM:bw_lim_events 8096119 #
number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 8096109 #
number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist #
Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 1964055138
+system.cpu.commit.COM:committed_per_cycle.samples 1964055004
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 1088074348 5539.94%
- 1 575643775 2930.89%
- 2 120435536 613.20%
- 3 120975808 615.95%
- 4 27955061 142.33%
- 5 8084154 41.16%
+ 0 1088074201 5539.94%
+ 1 575643784 2930.89%
+ 2 120435541 613.20%
+ 3 120975798 615.95%
+ 4 27955067 142.33%
+ 5 8084166 41.16%
6 10447088 53.19%
- 7 4343249 22.11%
- 8 8096119 41.22%
+ 7 4343250 22.11%
+ 8 8096109 41.22%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@@ -42,20 +42,20 @@
system.cpu.commit.branchMispredicts 83681535 #
The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489537508 #
The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243671 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 1390237691 #
The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 1390237652 #
The number of squashed insts skipped by commit
system.cpu.committedInsts 1405618365 #
Number of Instructions Simulated
system.cpu.committedInsts_total 1405618365 #
Number of Instructions Simulated
system.cpu.cpi 1.568931 #
CPI: Cycles Per Instruction
system.cpu.cpi_total 1.568931 #
CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 426261934 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14297.934404
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.549883
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 425346266 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 13092161000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_avg_miss_latency 14297.662769
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.135084
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 425346235 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 13092355500 #
number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002148 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 915668 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 667355 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1685933500
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses 915699 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 667386 #
number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1685830500
# number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 #
mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 248313 #
number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 #
number of SwapReq accesses(hits+misses)
@@ -69,48 +69,48 @@
system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 #
mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 40 #
number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166856630 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 37763.233543
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.301493
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 37763.269313
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.327068
# average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 164634096 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 83930070500 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 83930150000 #
number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.013320 #
miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 2222534 #
number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1870625 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 12696279000
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 12696288000
# number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 #
mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 351909 #
number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 1119.158506 #
Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 1119.158447 #
Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 #
number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 #
number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 #
number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
system.cpu.dcache.demand_accesses 593118564 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30916.502985 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23961.488416
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 589980362 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 97022231500 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 30916.284897 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23961.331807
# average overall mshr miss latency
+system.cpu.dcache.demand_hits 589980331 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 97022505500 #
number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005291 #
miss rate for demand accesses
-system.cpu.dcache.demand_misses 3138202 #
number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2537980 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 14382212500
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_misses 3138233 #
number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2538011 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 14382118500
# number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.001012 #
mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 600222 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 593118564 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30916.502985
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23961.488416
# average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 30916.284897
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23961.331807
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 589980362 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 97022231500 #
number of overall miss cycles
+system.cpu.dcache.overall_hits 589980331 #
number of overall hits
+system.cpu.dcache.overall_miss_latency 97022505500 #
number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005291 #
miss rate for overall accesses
-system.cpu.dcache.overall_misses 3138202 #
number of overall misses
-system.cpu.dcache.overall_mshr_hits 2537980 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 14382212500
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_misses 3138233 #
number of overall misses
+system.cpu.dcache.overall_mshr_hits 2538011 #
number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 14382118500
# number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.001012 #
mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 600222 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
@@ -119,44 +119,44 @@
system.cpu.dcache.sampled_refs 527374 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.579742 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 590215098 #
Total number of references to valid blocks.
+system.cpu.dcache.total_refs 590215067 #
Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 166150000 #
Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 348745 #
number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 416443424 #
Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 3435538867 #
Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 762668523 #
Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 782001807 #
Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 239759981 #
Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 2941384 #
Number of cycles decode is unblocking
-system.cpu.fetch.Branches 254458067 #
Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 354588627 #
Number of cache lines fetched
-system.cpu.fetch.Cycles 1199300776 #
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 10659934 #
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 3732201090 #
Number of instructions fetch has processed
+system.cpu.dcache.writebacks 348749 #
number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 416443317 #
Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 3435538799 #
Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 762668513 #
Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 782001789 #
Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 239759977 #
Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 2941385 #
Number of cycles decode is unblocking
+system.cpu.fetch.Branches 254458061 #
Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 354588619 #
Number of cache lines fetched
+system.cpu.fetch.Cycles 1199300749 #
Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 10659931 #
Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 3732201000 #
Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 88873600 #
Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.115384 #
Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 354588627 #
Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles 354588619 #
Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 182414509 #
Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.692364 #
Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of
instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 2203815119
+system.cpu.fetch.rateDist.samples 2203814981
system.cpu.fetch.rateDist.min_value 0
- 0 1359103013 6167.05%
- 1 256500552 1163.89%
+ 0 1359102894 6167.05%
+ 1 256500547 1163.89%
2 81150170 368.23%
3 38425919 174.36%
- 4 85384466 387.44%
- 5 41200028 186.95%
+ 4 85384463 387.44%
+ 5 41200023 186.95%
6 32567288 147.78%
7 20688755 93.88%
- 8 288794928 1310.43%
+ 8 288794922 1310.43%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 354588627 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses 354588619 #
number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 33291.255289
# average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059
# average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 354586500 #
number of ReadReq hits
+system.cpu.icache.ReadReq_hits 354586492 #
number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 70810500 #
number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000006 #
miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 2127 #
number of ReadReq misses
@@ -166,16 +166,16 @@
system.cpu.icache.ReadReq_mshr_misses 1379 #
number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>
# average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>
# average number of cycles each access was blocked
-system.cpu.icache.avg_refs 257319.666183 #
Average number of references to valid blocks.
+system.cpu.icache.avg_refs 257319.660377 #
Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0
# number of cycles access was blocked
system.cpu.icache.cache_copies 0 #
number of cache copies performed
-system.cpu.icache.demand_accesses 354588627 #
number of demand (read+write) accesses
+system.cpu.icache.demand_accesses 354588619 #
number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 33291.255289 #
average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059
# average overall mshr miss latency
-system.cpu.icache.demand_hits 354586500 #
number of demand (read+write) hits
+system.cpu.icache.demand_hits 354586492 #
number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 70810500 #
number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000006 #
miss rate for demand accesses
system.cpu.icache.demand_misses 2127 #
number of demand (read+write) misses
@@ -186,11 +186,11 @@
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 354588627 #
number of overall (read+write) accesses
+system.cpu.icache.overall_accesses 354588619 #
number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 33291.255289
# average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059
# average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>
# average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 354586500 #
number of overall hits
+system.cpu.icache.overall_hits 354586492 #
number of overall hits
system.cpu.icache.overall_miss_latency 70810500 #
number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000006 #
miss rate for overall accesses
system.cpu.icache.overall_misses 2127 #
number of overall misses
@@ -203,40 +203,40 @@
system.cpu.icache.replacements 222 #
number of replacements
system.cpu.icache.sampled_refs 1378 #
Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1057.993155 #
Cycle average of tags in use
-system.cpu.icache.total_refs 354586500 #
Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1057.993144 #
Cycle average of tags in use
+system.cpu.icache.total_refs 354586492 #
Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 #
number of writebacks
-system.cpu.idleCycles 1503210 #
Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 1503196 #
Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 128154505 #
Number of branches executed
system.cpu.iew.EXEC:nop 351416641 #
number of nop insts executed
system.cpu.iew.EXEC:rate 0.859194 #
Inst execution rate
system.cpu.iew.EXEC:refs 749485536 #
number of memory reference insts executed
system.cpu.iew.EXEC:stores 207432555 #
Number of stores executed
system.cpu.iew.EXEC:swp 0 #
number of swp insts executed
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