Hi, thanks for your interest in M5. I'd be happy to assist with solving some of these problems as updating and committing regressions for the MIPS O3 model has long been overdue on my part. I actually believed that we had fixed this earlier so I was a bit surprised to see this same error.
For your 1st error, Commenting that assertion is a good "stopgap" solution. I believe that error came from adding shadowsets functionality in M5. You can see the problem on line 180 of src/arch/mips/isa_traits.hh when NumShadowSets is set to 16 and then used in line 181 in calculating the NumIntRegs. I would say that there has to be a better way to define "ShadowSets" instead of hard-coding a constant value, so on a first-cut, I would fix that by changing line 181 to be: const int NumIntRegs = NumIntArchRegs+ NumIntSpecialRegs; //HI & LO Regs For your 2nd error, It seems that on a branch misprediction the speculative recovery is failing because the CPU wants to rollback to an instruction that was supposed to be squashed by a misprediction. This should be a quick fix, but I need a day to parse through the code and figure out what part is broken. It's a little tough given that the O3 works for different ISAs but I should be able to figure it out by tonite. Just in case you would like to help with some debugging in the future, here's what I will do to track down the problem: 1. Run the AtomicSimpleCPU model with the "Exec" flag on. 2. Run the O3 model with the "Exec" flag on. 3. After capturing both traces, use the m5/util/tracediff utility (or the diff command) to figure out which cycle number the instruction execution diverges at. 4. I'll re-run the O3 model a couple of hundred cycles back from the error point using the "--trace-start=X" option and also turn on the "O3CPUAll" (or maybe just the "O3CPU", "IEW" and "Fetch") flags. 5. *Hopefully* find the error quickly. I'll send out a patch with the fix and then commit it once everyone thinks its OK. Sorry for the problems this caused. Nothing in your setup seems to have broke things, it just looks like broken code. 2009/4/5 苟鹏飞 <[email protected]> > > Hello, everybody. > > We're very interesting in M5 simulator and wanna do something with such an > excellent tool. But, we find that the MIPS O3CPU model doesn't work well > because of some assertion faults. Firstly, the assertion information is as > follows: > > Assertion 'params->numPhysIntRegs >= numThreads * MipsISA::NumIntRegs' > > params->numPhysIntRegs equals 256 while MipsISA::NumIntRegs equals 521, so > it's obviously an fate error. After I change the value of numPhysIntRegs > from 256 to 1024, this assertion disappear, but there comes another > assertion fault as follows: > > Assertion 'pred_hist.front().seqNum == squashed_sn' > > I have no idea about this assertion. It looks like something goes wrong in > BTB, but i don't know what to do and how to solve it. > > Could anybody give some suggestion about this? Is a bug of mips o3cpu > model? or have i miss some steps when i run mips in o3 mode? > > Thank you guys. > > > > > ___________________________________________________________ > 好玩贺卡等你发，邮箱贺卡全新上线！ > http://card.mail.cn.yahoo.com/ > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > -- ---------- Korey L Sewell Graduate Student - PhD Candidate Computer Science & Engineering University of Michigan
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