>
> Thanks for your kind reply of this problem. You're so nice.
> Using the MIPS architecture on M5 for some system
> performance evaluation is our recent research interest. I
> will report on what we find for you, hope it useful for you
> and other developers to perfect the MIPS architecture on
> M5.
>
> Thanks for your kind reply again.
>
> Best wishes.
>
> --- 09年4月8日，周三, Korey Sewell <[email protected]>
> 写道：
>
> > 发件人: Korey Sewell <[email protected]>
> > 主题: Re: [m5-dev] MIPS O3 fault
> > 收件人: [email protected]
> > 日期: 2009年4月8日,周三,上午12:59
> > I looked into this closer and made some
> > progress but no permanent fix yet.
> >
> > It looks like adding the code for other ISAs
> > (x86,SPARC,etc.) broke the branch prediction in MIPS
> code. I
> > have to figure out a way to fix the MIPS things but
> > simultaneously keep everything else working.
> >
> >
> > This is nontrivial BUT I'm working on it. Using the
> > instruction traces I mentioned earlier, I'm starting
> to
> > track down some of the problems. I'll keep you posted
> on
> > the progress, but I should be done in a couple of
> days.
> >
> >
> > Thanks for your patience, I'll get it working again
> as
> > soon as possible.
> >
> > -korey
> >
> > 2009/4/5 苟鹏飞 <[email protected]>
> >
> >
> >
> > Hello, everybody.
> >
> >
> >
> > We're very interesting in M5 simulator and wanna do
> > something with such an excellent tool. But, we find
> that the
> > MIPS O3CPU model doesn't work well because of some
> > assertion faults. Firstly, the assertion information
> is as
> > follows:
> >
> >
> >
> >
> > Assertion 'params->numPhysIntRegs >= numThreads
> *
> > MipsISA::NumIntRegs'
> >
> >
> >
> > params->numPhysIntRegs equals 256 while
> > MipsISA::NumIntRegs equals 521, so it's obviously an
> > fate error. After I change the value of numPhysIntRegs
> from
> > 256 to 1024, this assertion disappear, but there
> comes
> > another assertion fault as follows:
> >
> >
> >
> >
> > Assertion 'pred_hist.front().seqNum ==
> > squashed_sn'
> >
> >
> >
> > I have no idea about this assertion. It looks like
> > something goes wrong in BTB, but i don't know what to
> do
> > and how to solve it.
> >
> >
> >
> > Could anybody give some suggestion about this? Is a
> bug of
> > mips o3cpu model? or have i miss some steps when i run
> mips
> > in o3 mode?
> >
> >
> >
> > Thank you guys.
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> ___________________________________________________________
> >
> >
> 好玩贺卡等你发，邮箱贺卡全新上线！
> >
> > http://card.mail.cn.yahoo.com/
> >
> > _______________________________________________
> >
> > m5-dev mailing list
> >
> > [email protected]
> >
> > http://m5sim.org/mailman/listinfo/m5-dev
> >
> >
> >
> >
> > --
> > ----------
> > Korey L Sewell
> > Graduate Student - PhD Candidate
> > Computer Science & Engineering
> > University of Michigan
> >
> >
>
>
>
> ___________________________________________________________
>
> 好玩贺卡等你发，邮箱贺卡全新上线！
>
> http://card.mail.cn.yahoo.com/
>
___________________________________________________________
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