changeset 47b4fcb10c11 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=47b4fcb10c11
description:
tlb: More fixing of unified TLB
diffstat:
20 files changed, 130 insertions(+), 129 deletions(-)
src/arch/alpha/AlphaTLB.py | 8 +++++-
src/arch/alpha/tlb.cc | 13 ++++------
src/arch/alpha/tlb.hh | 6 +----
src/arch/mips/tlb.cc | 12 ++++------
src/arch/mips/tlb.hh | 5 +---
src/arch/sparc/tlb.cc | 12 ++++------
src/arch/sparc/tlb.hh | 5 +---
src/arch/x86/faults.hh | 9 ++++---
src/arch/x86/pagetable_walker.cc | 18 +++++++--------
src/arch/x86/pagetable_walker.hh | 5 ++--
src/arch/x86/tlb.cc | 33 +++++++++++----------------
src/arch/x86/tlb.hh | 8 ++----
src/cpu/BaseCPU.py | 13 +++++-----
src/cpu/base_dyn_inst.hh | 5 ++--
src/cpu/o3/fetch_impl.hh | 2 -
src/cpu/simple/atomic.cc | 7 +++--
src/cpu/simple/timing.cc | 28 +++++++++++------------
src/cpu/simple/timing.hh | 45 +++++++++++++++++++++-----------------
src/sim/tlb.cc | 7 ++---
src/sim/tlb.hh | 18 +++++++++------
diffs (truncated from 738 to 300 lines):
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/alpha/AlphaTLB.py
--- a/src/arch/alpha/AlphaTLB.py Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/alpha/AlphaTLB.py Wed Apr 08 22:21:27 2009 -0700
@@ -34,4 +34,10 @@
class AlphaTLB(BaseTLB):
type = 'AlphaTLB'
cxx_class = 'AlphaISA::TLB'
- size = Param.Int(64, "TLB size")
+ size = Param.Int("TLB size")
+
+class AlphaDTB(AlphaTLB):
+ size = 64
+
+class AlphaITB(AlphaTLB):
+ size = 48
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/alpha/tlb.cc Wed Apr 08 22:21:27 2009 -0700
@@ -607,23 +607,20 @@
}
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
- if (execute)
+ if (mode == Execute)
return translateInst(req, tc);
else
- return translateData(req, tc, write);
+ return translateData(req, tc, mode == Write);
}
void
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation,
- bool write, bool execute)
+ Translation *translation, Mode mode)
{
assert(translation);
- translation->finish(translateAtomic(req, tc, write, execute),
- req, tc, write, execute);
+ translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
/* end namespace AlphaISA */ }
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/alpha/tlb.hh Wed Apr 08 22:21:27 2009 -0700
@@ -141,11 +141,9 @@
Fault translateInst(RequestPtr req, ThreadContext *tc);
public:
- Fault translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write = false, bool execute = false);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation,
- bool write = false, bool execute = false);
+ Translation *translation, Mode mode);
};
} // namespace AlphaISA
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/mips/tlb.cc Wed Apr 08 22:21:27 2009 -0700
@@ -562,22 +562,20 @@
}
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
- if (execute)
+ if (mode == Execute)
return translateInst(req, tc);
else
- return translateData(req, tc, write);
+ return translateData(req, tc, mode == Write);
}
void
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write, bool execute)
+ Translation *translation, Mode mode)
{
assert(translation);
- translation->finish(translateAtomic(req, tc, write, execute),
- req, tc, write, execute);
+ translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/mips/tlb.hh
--- a/src/arch/mips/tlb.hh Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/mips/tlb.hh Wed Apr 08 22:21:27 2009 -0700
@@ -138,10 +138,9 @@
void regStats();
- Fault translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write=false, bool execute=false);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write=false, bool execute=false);
+ Translation *translation, Mode mode);
private:
Fault translateInst(RequestPtr req, ThreadContext *tc);
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/sparc/tlb.cc Wed Apr 08 22:21:27 2009 -0700
@@ -843,22 +843,20 @@
};
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
- if (execute)
+ if (mode == Execute)
return translateInst(req, tc);
else
- return translateData(req, tc, write);
+ return translateData(req, tc, mode == Write);
}
void
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write, bool execute)
+ Translation *translation, Mode mode)
{
assert(translation);
- translation->finish(translateAtomic(req, tc, write, execute),
- req, tc, write, execute);
+ translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
#if FULL_SYSTEM
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/sparc/tlb.hh
--- a/src/arch/sparc/tlb.hh Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/sparc/tlb.hh Wed Apr 08 22:21:27 2009 -0700
@@ -163,10 +163,9 @@
void dumpAll();
- Fault translateAtomic(RequestPtr req,
- ThreadContext *tc, bool write=false, bool execute=false);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write=false, bool execute=false);
+ Translation *translation, Mode mode);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/x86/faults.hh
--- a/src/arch/x86/faults.hh Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/x86/faults.hh Wed Apr 08 22:21:27 2009 -0700
@@ -61,6 +61,7 @@
#include "base/bitunion.hh"
#include "base/misc.hh"
#include "sim/faults.hh"
+#include "sim/tlb.hh"
#include <string>
@@ -331,16 +332,16 @@
X86Fault("Page-Fault", "#PF", 14, _errorCode), addr(_addr)
{}
- PageFault(Addr _addr, bool present, bool write,
- bool user, bool reserved, bool fetch) :
+ PageFault(Addr _addr, bool present, BaseTLB::Mode mode,
+ bool user, bool reserved) :
X86Fault("Page-Fault", "#PF", 14, 0), addr(_addr)
{
PageFaultErrorCode code = 0;
code.present = present;
- code.write = write;
+ code.write = (mode == BaseTLB::Write);
code.user = user;
code.reserved = reserved;
- code.fetch = fetch;
+ code.fetch = (mode == BaseTLB::Execute);
errorCode = code;
}
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/x86/pagetable_walker.cc
--- a/src/arch/x86/pagetable_walker.cc Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/x86/pagetable_walker.cc Wed Apr 08 22:21:27 2009 -0700
@@ -98,7 +98,7 @@
bool uncacheable = pte.pcd;
Addr nextRead = 0;
bool doWrite = false;
- bool badNX = pte.nx && execute && enableNX;
+ bool badNX = pte.nx && mode == BaseTLB::Write && enableNX;
switch(state) {
case LongPML4:
DPRINTF(PageTableWalker,
@@ -329,14 +329,13 @@
Fault
Walker::start(ThreadContext * _tc, BaseTLB::Translation *_translation,
- RequestPtr _req, bool _write, bool _execute)
+ RequestPtr _req, BaseTLB::Mode _mode)
{
assert(state == Ready);
tc = _tc;
req = _req;
Addr vaddr = req->getVaddr();
- execute = _execute;
- write = _write;
+ mode = _mode;
translation = _translation;
VAddr addr = vaddr;
@@ -451,14 +450,14 @@
* well.
*/
bool delayedResponse;
- Fault fault = tlb->translate(req, tc, NULL, write, execute,
+ Fault fault = tlb->translate(req, tc, NULL, mode,
delayedResponse, true);
assert(!delayedResponse);
// Let the CPU continue.
- translation->finish(fault, req, tc, write);
+ translation->finish(fault, req, tc, mode);
} else {
// There was a fault during the walk. Let the CPU know.
- translation->finish(timingFault, req, tc, write);
+ translation->finish(timingFault, req, tc, mode);
}
}
} else if (pkt->wasNacked()) {
@@ -563,8 +562,9 @@
{
DPRINTF(PageTableWalker, "Raising page fault.\n");
HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
- return new PageFault(entry.vaddr, present, write,
- m5reg.cpl == 3, false, execute && enableNX);
+ if (mode == BaseTLB::Execute && !enableNX)
+ mode = BaseTLB::Read;
+ return new PageFault(entry.vaddr, present, mode, m5reg.cpl == 3, false);
}
}
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/x86/pagetable_walker.hh
--- a/src/arch/x86/pagetable_walker.hh Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/x86/pagetable_walker.hh Wed Apr 08 22:21:27 2009 -0700
@@ -97,7 +97,7 @@
// Kick off the state machine.
Fault start(ThreadContext * _tc, BaseTLB::Translation *translation,
- RequestPtr req, bool write, bool execute);
+ RequestPtr req, BaseTLB::Mode mode);
// Clean up after the state machine.
void
stop()
@@ -183,7 +183,8 @@
State nextState;
int size;
bool enableNX;
- bool write, execute, user;
+ BaseTLB::Mode mode;
+ bool user;
TlbEntry entry;
Fault pageFault(bool present);
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/x86/tlb.cc Wed Apr 08 22:21:27 2009 -0700
@@ -186,9 +186,8 @@
}
Fault
-TLB::translate(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write, bool execute,
- bool &delayedResponse, bool timing)
+TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
+ Mode mode, bool &delayedResponse, bool timing)
{
delayedResponse = false;
Addr vaddr = req->getVaddr();
@@ -577,9 +576,9 @@
bool expandDown = false;
SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
- if (!attr.writable && write)
+ if (!attr.writable && mode == Write)
return new GeneralProtection(0);
- if (!attr.readable && !write && !execute)
+ if (!attr.readable && mode == Read)
return new GeneralProtection(0);
expandDown = attr.expandDown;
@@ -612,8 +611,7 @@
TlbEntry *entry = lookup(vaddr);
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