changeset 0555121b5c5f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0555121b5c5f
description:
tests: update tests for TLB unification
diffstat:
197 files changed, 1885 insertions(+), 1171 deletions(-)
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
| 4
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
| 8
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
| 40 +-
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
| 4
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
| 10
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
| 40 +-
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
| 4
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
| 10
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
| 40 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
| 4
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
| 8
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
| 8
tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
| 4
tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
| 10
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
| 8
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
| 4
tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
| 8
tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
| 8
tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
| 4
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
| 10
tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
| 8
tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
| 4
tests/long/00.gzip/ref/x86/linux/simple-timing/simout
| 10
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
| 8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
| 8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
| 8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
| 72 +++--
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
| 4
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
| 8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
| 40 +-
tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
| 4
tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
| 10
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
| 8
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
| 4
tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
| 8
tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
| 8
tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
| 4
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
| 10
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
| 8
tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
| 4
tests/long/10.mcf/ref/x86/linux/simple-timing/simout
| 10
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
| 8
tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
| 4
tests/long/20.parser/ref/x86/linux/simple-atomic/simout
| 10
tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
| 8
tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
| 4
tests/long/20.parser/ref/x86/linux/simple-timing/simout
| 10
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
| 8
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
| 4
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
| 8
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
| 40 +-
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
| 4
tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
| 10
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
| 40 +-
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
| 4
tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
| 10
tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
| 40 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
| 4
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
| 8
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
| 40 +-
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
| 4
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
| 10
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
| 40 +-
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
| 4
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
| 10
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
| 40 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
| 4
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
| 8
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
| 40 +-
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
| 4
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
| 10
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
| 40 +-
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
| 4
tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
| 10
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
| 40 +-
tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
| 4
tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
| 10
tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
| 8
tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
| 4
tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
| 8
tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
| 8
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
| 4
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
| 8
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
| 40 +-
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
| 4
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
| 10
tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
| 40 +-
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
| 4
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
| 10
tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
| 40 +-
tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
| 4
tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
| 10
tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
| 8
tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
| 4
tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
| 10
tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
| 8
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
| 4
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
| 8
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
| 40 +-
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
| 4
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
| 10
tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
| 40 +-
tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
| 4
tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
| 10
tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
| 40 +-
tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
| 4
tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
| 10
tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
| 8
tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
| 4
tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
| 12
tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
| 8
tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
| 4
tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
| 12
tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
| 8
tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
| 4
tests/long/70.twolf/ref/x86/linux/simple-timing/simout
| 12
tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
| 8
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
| 4
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
| 10
tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
| 8
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
| 4
tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
| 8
tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
| 40 +-
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
| 4
tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
| 10
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
| 38 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
| 4
tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
| 10
tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
| 40 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
| 4
tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
| 8
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
| 40 +-
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
| 4
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
| 10
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
| 40 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
| 4
tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
| 10
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
| 40 +-
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
| 12
tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
| 10
tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
| 26 -
tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
| 12
tests/quick/00.hello/ref/mips/linux/simple-timing/simout
| 10
tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
| 26 -
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
| 4
tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
| 10
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
| 8
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
| 4
tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
| 10
tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
| 8
tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
| 4
tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
| 10
tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
| 8
tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
| 4
tests/quick/00.hello/ref/x86/linux/simple-timing/simout
| 10
tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
| 8
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
| 4
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
| 8
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
| 40 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
| 4
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
| 8
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
| 8
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
| 4
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
| 10
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
| 8
tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
| 4
tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
| 10
tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
| 8
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
| 8
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
| 10
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
| 72 +++--
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
| 4
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
| 10
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
| 40 +-
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
| 8
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
| 10
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
| 72 +++--
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
| 4
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
| 10
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
| 40 +-
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
| 4
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
| 10
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
| 40 +-
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
| 4
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
| 10
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
| 40 +-
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
| 16 -
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
| 10
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
| 136 +++++++--
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
| 16 -
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
| 10
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
| 136 +++++++--
tests/quick/50.memtest/ref/alpha/linux/memtest/simout
| 10
tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
| 6
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
| 12
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
| 10
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
| 142 +++++++---
diffs (truncated from 6201 to 300 lines):
diff -r 47b4fcb10c11 -r 0555121b5c5f
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Wed Apr 08
22:21:27 2009 -0700
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Wed Apr 08
22:21:30 2009 -0700
@@ -132,7 +132,7 @@
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.fuPool]
@@ -305,7 +305,7 @@
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.l2cache]
diff -r 47b4fcb10c11 -r 0555121b5c5f
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Wed Apr 08
22:21:27 2009 -0700
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Wed Apr 08
22:21:30 2009 -0700
@@ -5,11 +5,11 @@
All Rights Reserved
-M5 compiled Mar 6 2009 18:15:46
-M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip
-M5 started Mar 6 2009 18:15:58
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:37:48
M5 executing on maize
-command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d
/n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
-re tests/run.py long/00.gzip/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff -r 47b4fcb10c11 -r 0555121b5c5f
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Wed Apr 08
22:21:27 2009 -0700
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Wed Apr 08
22:21:30 2009 -0700
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 309694 #
Simulator instruction rate (inst/s)
-host_mem_usage 206028 #
Number of bytes of host memory used
-host_seconds 1826.17 #
Real time elapsed on the host
-host_tick_rate 91491135 #
Simulator tick rate (ticks/s)
+host_inst_rate 312901 #
Simulator instruction rate (inst/s)
+host_mem_usage 206004 #
Number of bytes of host memory used
+host_seconds 1807.45 #
Real time elapsed on the host
+host_tick_rate 92438667 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 565552443 #
Number of instructions simulated
sim_seconds 0.167078 #
Number of seconds simulated
@@ -123,10 +123,14 @@
system.cpu.decode.DECODE:SquashCycles 9869862 #
Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 2004 #
Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 5413191 #
Number of cycles decode is unblocking
-system.cpu.dtb.accesses 163077390 #
DTB accesses
-system.cpu.dtb.acv 0 #
DTB access violations
-system.cpu.dtb.hits 163013880 #
DTB hits
-system.cpu.dtb.misses 63510 #
DTB misses
+system.cpu.dtb.data_accesses 163077390 #
DTB accesses
+system.cpu.dtb.data_acv 0 #
DTB access violations
+system.cpu.dtb.data_hits 163013880 #
DTB hits
+system.cpu.dtb.data_misses 63510 #
DTB misses
+system.cpu.dtb.fetch_accesses 0 #
ITB accesses
+system.cpu.dtb.fetch_acv 0 #
ITB acv
+system.cpu.dtb.fetch_hits 0 #
ITB hits
+system.cpu.dtb.fetch_misses 0 #
ITB misses
system.cpu.dtb.read_accesses 122284109 #
DTB read accesses
system.cpu.dtb.read_acv 0 #
DTB read access violations
system.cpu.dtb.read_hits 122260496 #
DTB read hits
@@ -319,10 +323,22 @@
system.cpu.iq.iqSquashedInstsIssued 12833 #
Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 6 #
Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 29313548 #
Number of squashed operands that are examined and possibly removed from graph
-system.cpu.itb.accesses 66014446 #
ITB accesses
-system.cpu.itb.acv 0 #
ITB acv
-system.cpu.itb.hits 66014406 #
ITB hits
-system.cpu.itb.misses 40 #
ITB misses
+system.cpu.itb.data_accesses 0 #
DTB accesses
+system.cpu.itb.data_acv 0 #
DTB access violations
+system.cpu.itb.data_hits 0 #
DTB hits
+system.cpu.itb.data_misses 0 #
DTB misses
+system.cpu.itb.fetch_accesses 66014446 #
ITB accesses
+system.cpu.itb.fetch_acv 0 #
ITB acv
+system.cpu.itb.fetch_hits 66014406 #
ITB hits
+system.cpu.itb.fetch_misses 40 #
ITB misses
+system.cpu.itb.read_accesses 0 #
DTB read accesses
+system.cpu.itb.read_acv 0 #
DTB read access violations
+system.cpu.itb.read_hits 0 #
DTB read hits
+system.cpu.itb.read_misses 0 #
DTB read misses
+system.cpu.itb.write_accesses 0 #
DTB write accesses
+system.cpu.itb.write_acv 0 #
DTB write access violations
+system.cpu.itb.write_hits 0 #
DTB write hits
+system.cpu.itb.write_misses 0 #
DTB write misses
system.cpu.l2cache.ReadExReq_accesses 256647 #
number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026
# average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767
# average ReadExReq mshr miss latency
diff -r 47b4fcb10c11 -r 0555121b5c5f
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini Wed Apr
08 22:21:27 2009 -0700
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini Wed Apr
08 22:21:30 2009 -0700
@@ -39,11 +39,11 @@
icache_port=system.membus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.tracer]
diff -r 47b4fcb10c11 -r 0555121b5c5f
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout Wed Apr 08
22:21:27 2009 -0700
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout Wed Apr 08
22:21:30 2009 -0700
@@ -5,11 +5,11 @@
All Rights Reserved
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:27:51
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re
tests/run.py long/00.gzip/alpha/tru64/simple-atomic
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:34:49
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re
tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff -r 47b4fcb10c11 -r 0555121b5c5f
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt Wed Apr
08 22:21:27 2009 -0700
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt Wed Apr
08 22:21:30 2009 -0700
@@ -1,17 +1,21 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 6175770 #
Simulator instruction rate (inst/s)
-host_mem_usage 195684 #
Number of bytes of host memory used
-host_seconds 97.45 #
Real time elapsed on the host
-host_tick_rate 3087904278 #
Simulator tick rate (ticks/s)
+host_inst_rate 5975527 #
Simulator instruction rate (inst/s)
+host_mem_usage 197448 #
Number of bytes of host memory used
+host_seconds 100.72 #
Real time elapsed on the host
+host_tick_rate 2987780856 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 601856964 #
Number of instructions simulated
sim_seconds 0.300931 #
Number of seconds simulated
sim_ticks 300930958000 #
Number of ticks simulated
-system.cpu.dtb.accesses 153970296 #
DTB accesses
-system.cpu.dtb.acv 0 #
DTB access violations
-system.cpu.dtb.hits 153965363 #
DTB hits
-system.cpu.dtb.misses 4933 #
DTB misses
+system.cpu.dtb.data_accesses 153970296 #
DTB accesses
+system.cpu.dtb.data_acv 0 #
DTB access violations
+system.cpu.dtb.data_hits 153965363 #
DTB hits
+system.cpu.dtb.data_misses 4933 #
DTB misses
+system.cpu.dtb.fetch_accesses 0 #
ITB accesses
+system.cpu.dtb.fetch_acv 0 #
ITB acv
+system.cpu.dtb.fetch_hits 0 #
ITB hits
+system.cpu.dtb.fetch_misses 0 #
ITB misses
system.cpu.dtb.read_accesses 114516673 #
DTB read accesses
system.cpu.dtb.read_acv 0 #
DTB read access violations
system.cpu.dtb.read_hits 114514042 #
DTB read hits
@@ -21,10 +25,22 @@
system.cpu.dtb.write_hits 39451321 #
DTB write hits
system.cpu.dtb.write_misses 2302 #
DTB write misses
system.cpu.idle_fraction 0 #
Percentage of idle cycles
-system.cpu.itb.accesses 601861917 #
ITB accesses
-system.cpu.itb.acv 0 #
ITB acv
-system.cpu.itb.hits 601861897 #
ITB hits
-system.cpu.itb.misses 20 #
ITB misses
+system.cpu.itb.data_accesses 0 #
DTB accesses
+system.cpu.itb.data_acv 0 #
DTB access violations
+system.cpu.itb.data_hits 0 #
DTB hits
+system.cpu.itb.data_misses 0 #
DTB misses
+system.cpu.itb.fetch_accesses 601861917 #
ITB accesses
+system.cpu.itb.fetch_acv 0 #
ITB acv
+system.cpu.itb.fetch_hits 601861897 #
ITB hits
+system.cpu.itb.fetch_misses 20 #
ITB misses
+system.cpu.itb.read_accesses 0 #
DTB read accesses
+system.cpu.itb.read_acv 0 #
DTB read access violations
+system.cpu.itb.read_hits 0 #
DTB read hits
+system.cpu.itb.read_misses 0 #
DTB read misses
+system.cpu.itb.write_accesses 0 #
DTB write accesses
+system.cpu.itb.write_acv 0 #
DTB write access violations
+system.cpu.itb.write_hits 0 #
DTB write hits
+system.cpu.itb.write_misses 0 #
DTB write misses
system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
system.cpu.numCycles 601861917 #
number of cpu cycles simulated
system.cpu.num_insts 601856964 #
Number of instructions executed
diff -r 47b4fcb10c11 -r 0555121b5c5f
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini Wed Apr
08 22:21:27 2009 -0700
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini Wed Apr
08 22:21:30 2009 -0700
@@ -68,7 +68,7 @@
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.dtb]
-type=AlphaDTB
+type=AlphaTLB
size=64
[system.cpu.icache]
@@ -104,7 +104,7 @@
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.itb]
-type=AlphaITB
+type=AlphaTLB
size=48
[system.cpu.l2cache]
diff -r 47b4fcb10c11 -r 0555121b5c5f
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout Wed Apr 08
22:21:27 2009 -0700
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout Wed Apr 08
22:21:30 2009 -0700
@@ -5,11 +5,11 @@
All Rights Reserved
-M5 compiled Feb 16 2009 00:22:05
-M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
-M5 started Feb 16 2009 00:27:51
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re
tests/run.py long/00.gzip/alpha/tru64/simple-timing
+M5 compiled Apr 8 2009 12:30:02
+M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff
+M5 started Apr 8 2009 12:34:42
+M5 executing on maize
+command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re
tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff -r 47b4fcb10c11 -r 0555121b5c5f
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt Wed Apr
08 22:21:27 2009 -0700
+++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt Wed Apr
08 22:21:30 2009 -0700
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1969135 #
Simulator instruction rate (inst/s)
-host_mem_usage 203124 #
Number of bytes of host memory used
-host_seconds 305.65 #
Real time elapsed on the host
-host_tick_rate 2545444210 #
Simulator tick rate (ticks/s)
+host_inst_rate 3011769 #
Simulator instruction rate (inst/s)
+host_mem_usage 204988 #
Number of bytes of host memory used
+host_seconds 199.84 #
Real time elapsed on the host
+host_tick_rate 3893225431 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 601856964 #
Number of instructions simulated
sim_seconds 0.778004 #
Number of seconds simulated
@@ -71,10 +71,14 @@
system.cpu.dcache.total_refs 153509968 #
Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 579204000 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 325723 #
number of writebacks
-system.cpu.dtb.accesses 153970296 #
DTB accesses
-system.cpu.dtb.acv 0 #
DTB access violations
-system.cpu.dtb.hits 153965363 #
DTB hits
-system.cpu.dtb.misses 4933 #
DTB misses
+system.cpu.dtb.data_accesses 153970296 #
DTB accesses
+system.cpu.dtb.data_acv 0 #
DTB access violations
+system.cpu.dtb.data_hits 153965363 #
DTB hits
+system.cpu.dtb.data_misses 4933 #
DTB misses
+system.cpu.dtb.fetch_accesses 0 #
ITB accesses
+system.cpu.dtb.fetch_acv 0 #
ITB acv
+system.cpu.dtb.fetch_hits 0 #
ITB hits
+system.cpu.dtb.fetch_misses 0 #
ITB misses
system.cpu.dtb.read_accesses 114516673 #
DTB read accesses
system.cpu.dtb.read_acv 0 #
DTB read access violations
system.cpu.dtb.read_hits 114514042 #
DTB read hits
@@ -137,10 +141,22 @@
system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 #
number of writebacks
system.cpu.idle_fraction 0 #
Percentage of idle cycles
-system.cpu.itb.accesses 601861918 #
ITB accesses
-system.cpu.itb.acv 0 #
ITB acv
-system.cpu.itb.hits 601861898 #
ITB hits
-system.cpu.itb.misses 20 #
ITB misses
+system.cpu.itb.data_accesses 0 #
DTB accesses
+system.cpu.itb.data_acv 0 #
DTB access violations
+system.cpu.itb.data_hits 0 #
DTB hits
+system.cpu.itb.data_misses 0 #
DTB misses
+system.cpu.itb.fetch_accesses 601861918 #
ITB accesses
+system.cpu.itb.fetch_acv 0 #
ITB acv
+system.cpu.itb.fetch_hits 601861898 #
ITB hits
+system.cpu.itb.fetch_misses 20 #
ITB misses
+system.cpu.itb.read_accesses 0 #
DTB read accesses
+system.cpu.itb.read_acv 0 #
DTB read access violations
+system.cpu.itb.read_hits 0 #
DTB read hits
+system.cpu.itb.read_misses 0 #
DTB read misses
+system.cpu.itb.write_accesses 0 #
DTB write accesses
+system.cpu.itb.write_acv 0 #
DTB write access violations
+system.cpu.itb.write_hits 0 #
DTB write hits
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