changeset 0aa0a6189767 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0aa0a6189767
description:
X86: Implement the load machine status word instruction (LMSW).
diffstat:
2 files changed, 38 insertions(+), 2 deletions(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa | 4 +-
src/arch/x86/isa/insts/system/control_registers.py | 36 ++++++++++++++++++++
diffs (65 lines):
diff -r aa9ca21a9af4 -r 0aa0a6189767
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Sun Apr 19 03:14:33
2009 -0700
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Sun Apr 19 03:17:14
2009 -0700
@@ -126,7 +126,7 @@
0x7: invlpga();
}
0x4: smsw_Rv();
- 0x6: lmsw_Rv();
+ 0x6: Inst::LMSW(Rv);
0x7: decode MODRM_RM {
0x0: Inst::SWAPGS();
0x1: rdtscp();
@@ -156,7 +156,7 @@
}
}
0x4: smsw_Mw();
- 0x6: lmsw_Mw();
+ 0x6: Inst::LMSW(Mw);
0x7: Inst::INVLPG(M);
default: Inst::UD2();
}
diff -r aa9ca21a9af4 -r 0aa0a6189767
src/arch/x86/isa/insts/system/control_registers.py
--- a/src/arch/x86/isa/insts/system/control_registers.py Sun Apr 19
03:14:33 2009 -0700
+++ b/src/arch/x86/isa/insts/system/control_registers.py Sun Apr 19
03:17:14 2009 -0700
@@ -32,4 +32,40 @@
andi t1, t1, 0xF7, dataSize=1
wrcr 0, t1, dataSize=8
};
+
+def macroop LMSW_R {
+ rdcr t1, 0, dataSize=8
+ # This logic sets MP, EM, and TS to whatever is in the operand. It will
+ # set PE but not clear it.
+ limm t2, "~ULL(0xe)", dataSize=8
+ and t1, t1, t2, dataSize=8
+ andi t2, reg, 0xf, dataSize=8
+ or t1, t1, t2, dataSize=8
+ wrcr 0, t1, dataSize=8
+};
+
+def macroop LMSW_M {
+ ld t3, seg, sib, disp, dataSize=2
+ rdcr t1, 0, dataSize=8
+ # This logic sets MP, EM, and TS to whatever is in the operand. It will
+ # set PE but not clear it.
+ limm t2, "~ULL(0xe)", dataSize=8
+ and t1, t1, t2, dataSize=8
+ andi t2, t3, 0xf, dataSize=8
+ or t1, t1, t2, dataSize=8
+ wrcr 0, t1, dataSize=8
+};
+
+def macroop LMSW_P {
+ rdip t7, dataSize=asz
+ ld t3, seg, riprel, disp, dataSize=2
+ rdcr t1, 0, dataSize=8
+ # This logic sets MP, EM, and TS to whatever is in the operand. It will
+ # set PE but not clear it.
+ limm t2, "~ULL(0xe)", dataSize=8
+ and t1, t1, t2, dataSize=8
+ andi t2, t3, 0xf, dataSize=8
+ or t1, t1, t2, dataSize=8
+ wrcr 0, t1, dataSize=8
+};
'''
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
