changeset 40bdbc32e3db in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=40bdbc32e3db
description:
X86: Implement the save machine status word instruction (SMSW).
diffstat:
2 files changed, 17 insertions(+), 2 deletions(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa | 4 ++--
src/arch/x86/isa/insts/system/control_registers.py | 15 +++++++++++++++
diffs (44 lines):
diff -r 0aa0a6189767 -r 40bdbc32e3db
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Sun Apr 19 03:17:14
2009 -0700
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Sun Apr 19 03:22:38
2009 -0700
@@ -125,7 +125,7 @@
0x6: skinit();
0x7: invlpga();
}
- 0x4: smsw_Rv();
+ 0x4: Inst::SMSW(Rv);
0x6: Inst::LMSW(Rv);
0x7: decode MODRM_RM {
0x0: Inst::SWAPGS();
@@ -155,7 +155,7 @@
default: Inst::LIDT(M);
}
}
- 0x4: smsw_Mw();
+ 0x4: Inst::SMSW(Mw);
0x6: Inst::LMSW(Mw);
0x7: Inst::INVLPG(M);
default: Inst::UD2();
diff -r 0aa0a6189767 -r 40bdbc32e3db
src/arch/x86/isa/insts/system/control_registers.py
--- a/src/arch/x86/isa/insts/system/control_registers.py Sun Apr 19
03:17:14 2009 -0700
+++ b/src/arch/x86/isa/insts/system/control_registers.py Sun Apr 19
03:22:38 2009 -0700
@@ -68,4 +68,19 @@
or t1, t1, t2, dataSize=8
wrcr 0, t1, dataSize=8
};
+
+def macroop SMSW_R {
+ rdcr reg, 0
+};
+
+def macroop SMSW_M {
+ rdcr t1, 0
+ st t1, seg, sib, disp, dataSize=2
+};
+
+def macroop SMSW_P {
+ rdcr t1, 0
+ rdip t7, dataSize=asz
+ st t1, seg, riprel, disp, dataSize=2
+};
'''
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