So in the In-Order CPU, the current configuration reads the source registers for an instruction in stages prior to Execute. The way the model is specified, you can define your pipeline to read source registers (and stall if not available) at an arbitrary stage so I'm a fan of this general flexibility.
In testing FP registers in M5 (particularly the eon regression), I've come to find this is a problem because to accurately read the source FP registers I need to know if it's a 32-bit or 64-bit value to be read. This is generally irrelevant for int registers because they are all 32 bit values. Also, I think this might be important for ISAs that model double precision FP by using 2 registers. What could happen in a multithreaded environment (like O3-SMT) is that you could be running one thread that is using single precision op and another thread that is using double precision ops. It would be up to the CPU to allocate registers appropriately but without knowledge of if an FP operands width early, then you could potentially mess up allocation here (I dont think O3 handles this situation or does it?) The solution I'm thinking of will potentially cause some push-back, so I'm bringing it up here now while I brainstorm on what to do. So here goes my thought process: I think I need something in StaticInst similar to srcRegIdx() to ask for the source register width. Maybe something like srcRegWidth() would work. The mechanisms to get that working are somewhat in place because somewhere in isa_parser.py/decoder.isa the width of operands is kept so that we get this right in the auto-generated "execute()" functions. I figure if the _srcRegIdx values are autogenerated, why not autogenerate _srcRegWidth values *only* for FP ops so that just like an instruction can say "inst->srcRegIdx()", i can also say "inst-srcRegWidth()". Seems like this would be a solution that fits in with how the instructions are accessed anyway so it wont be too intrusive. The cost of adding that could be low as well, considering that instead of adding an actual integer value to keep the width, this could just be a boolean variable (32 or 64 bit) to hold the possible widths (or maybe just use bitsets and set a flag there). So that would be my first cut solution to the problem. Thoughts and ideas are welcome. =========== Korey L Sewell PhD Candidate Computer Science & Engineering University of Michigan _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
