> Actually it does because -all- floating point registers are then 32 bits. > The existence of 64 bit registers is just an illusion the instructions > provide by gluing two 32 bit registers together internally. I understand that for MIPS/SPARC, but does the same hold true for Alpha?
I'm encountering an issue where the instruction is "divt f1,f0,f0" >From looking at the generated output, alpha is expected both f1 and f0 to be double precision registers. Whereas, in say MIPS/SPARC, when you say f0, you really mean f0+f1. Or am I just misinterpreting how alpha is working? Guess I need to double check, but I thought the above holds... -- =========== Korey L Sewell PhD Candidate Computer Science & Engineering University of Michigan _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
