changeset 19fedb1e5ded in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=19fedb1e5ded
description:
inorder/alpha-isa: create eaComp object visible to StaticInst through
ISA
Remove subinstructions eaComp/memAcc since unused in CPU Models.
Instead, create eaComp that is visible from StaticInst object. Gives InOrder
model capability of generating address without actually initiating access
* * *
diffstat:
5 files changed, 39 insertions(+), 221 deletions(-)
src/arch/alpha/isa/mem.isa | 226 +++--------------------------------
src/arch/alpha/isa/pal.isa | 11 -
src/cpu/SConscript | 4
src/cpu/inorder/inorder_dyn_inst.cc | 16 +-
src/cpu/inorder/pipeline_traits.cc | 3
diffs (truncated from 440 to 300 lines):
diff -r 1a8950d566ff -r 19fedb1e5ded src/arch/alpha/isa/mem.isa
--- a/src/arch/alpha/isa/mem.isa Tue May 12 15:01:14 2009 -0400
+++ b/src/arch/alpha/isa/mem.isa Tue May 12 15:01:14 2009 -0400
@@ -44,27 +44,17 @@
/// Memory request flags. See mem_req_base.hh.
Request::Flags memAccessFlags;
- /// Pointer to EAComp object.
- const StaticInstPtr eaCompPtr;
- /// Pointer to MemAcc object.
- const StaticInstPtr memAccPtr;
/// Constructor
- Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- StaticInstPtr _eaCompPtr = nullStaticInstPtr,
- StaticInstPtr _memAccPtr = nullStaticInstPtr)
- : AlphaStaticInst(mnem, _machInst, __opClass),
- eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
+ Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
+ : AlphaStaticInst(mnem, _machInst, __opClass)
{
}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- public:
-
- const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
- const StaticInstPtr &memAccInst() const { return memAccPtr; }
+ public:
Request::Flags memAccFlags() { return memAccessFlags; }
};
@@ -80,10 +70,8 @@
int32_t disp;
/// Constructor.
- MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass
__opClass,
- StaticInstPtr _eaCompPtr = nullStaticInstPtr,
- StaticInstPtr _memAccPtr = nullStaticInstPtr)
- : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
+ MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass
__opClass)
+ : Memory(mnem, _machInst, __opClass),
disp(MEMDISP)
{
}
@@ -99,10 +87,8 @@
{
protected:
/// Constructor
- MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass
__opClass,
- StaticInstPtr _eaCompPtr = nullStaticInstPtr,
- StaticInstPtr _memAccPtr = nullStaticInstPtr)
- : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
+ MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass
__opClass)
+ : Memory(mnem, _machInst, __opClass)
{
}
@@ -142,32 +128,6 @@
*/
class %(class_name)s : public %(base_class)s
{
- protected:
-
- /**
- * "Fake" effective address computation class for "%(mnemonic)s".
- */
- class EAComp : public %(base_class)s
- {
- public:
- /// Constructor
- EAComp(ExtMachInst machInst);
-
- %(BasicExecDeclare)s
- };
-
- /**
- * "Fake" memory access instruction class for "%(mnemonic)s".
- */
- class MemAcc : public %(base_class)s
- {
- public:
- /// Constructor
- MemAcc(ExtMachInst machInst);
-
- %(BasicExecDeclare)s
- };
-
public:
/// Constructor.
@@ -175,6 +135,8 @@
%(BasicExecDeclare)s
+ %(EACompDeclare)s
+
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
@@ -184,6 +146,10 @@
}};
+def template EACompDeclare {{
+ Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
def template InitiateAccDeclare {{
Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
@@ -214,41 +180,18 @@
}
}};
-def template EACompConstructor {{
- /** TODO: change op_class to AddrGenOp or something (requires
- * creating new member of OpClass enum in op_class.hh, updating
- * config files, etc.). */
- inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
- : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
+
+def template LoadStoreConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(constructor)s;
}
}};
-
-def template MemAccConstructor {{
- inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
- : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
- {
- %(constructor)s;
- }
-}};
-
-
-def template LoadStoreConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
- : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- new EAComp(machInst), new MemAcc(machInst))
- {
- %(constructor)s;
- }
-}};
-
-
def template EACompExecute {{
- Fault
- %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
+ Fault %(class_name)s::eaComp(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -267,32 +210,6 @@
}
}};
-def template LoadMemAccExecute {{
- Fault
- %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Addr EA;
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- EA = xc->getEA();
-
- if (fault == NoFault) {
- fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
- %(memacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
def template LoadExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
@@ -366,78 +283,6 @@
}};
-def template StoreMemAccExecute {{
- Fault
- %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Addr EA;
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- EA = xc->getEA();
-
- if (fault == NoFault) {
- %(memacc_code)s;
- }
-
- if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
- }
-
- if (fault == NoFault) {
- %(postacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-def template StoreCondMemAccExecute {{
- Fault
- %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Addr EA;
- Fault fault = NoFault;
- uint64_t write_result = 0;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- EA = xc->getEA();
-
- if (fault == NoFault) {
- %(memacc_code)s;
- }
-
- if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, &write_result);
- if (traceData) { traceData->setData(Mem); }
- }
-
- if (fault == NoFault) {
- %(postacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-
def template StoreExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
@@ -582,26 +427,6 @@
}};
-def template MiscMemAccExecute {{
- Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
- Addr EA;
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- EA = xc->getEA();
-
- if (fault == NoFault) {
- %(memacc_code)s;
- }
-
- return NoFault;
- }
-}};
-
def template MiscExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
