changeset f51edf04e4a1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f51edf04e4a1
description:
inorder-miscregs: Fix indexing for misc. reg operands and update
result-types for better tracing of these types of values
diffstat:
6 files changed, 115 insertions(+), 47 deletions(-)
src/cpu/inorder/cpu.hh | 1
src/cpu/inorder/inorder_dyn_inst.cc | 63 +++++++++++++++++----------
src/cpu/inorder/inorder_dyn_inst.hh | 46 ++++++++++++++++++-
src/cpu/inorder/resources/cache_unit.cc | 5 +-
src/cpu/inorder/resources/execution_unit.cc | 15 +++---
src/cpu/inorder/resources/use_def.cc | 32 ++++++++-----
diffs (truncated from 368 to 300 lines):
diff -r 19fedb1e5ded -r f51edf04e4a1 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Tue May 12 15:01:14 2009 -0400
+++ b/src/cpu/inorder/cpu.hh Tue May 12 15:01:14 2009 -0400
@@ -247,6 +247,7 @@
/** The Pipeline Stages for the CPU */
PipelineStage *pipelineStage[ThePipeline::NumStages];
+ /** Program Counters */
TheISA::IntReg PC[ThePipeline::MaxThreads];
TheISA::IntReg nextPC[ThePipeline::MaxThreads];
TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
diff -r 19fedb1e5ded -r f51edf04e4a1 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Tue May 12 15:01:14 2009 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Tue May 12 15:01:14 2009 -0400
@@ -359,7 +359,7 @@
InOrderDynInst::setFloatSrc(int idx, FloatReg val, int width)
{
if (width == 32)
- instSrc[idx].fp = val;
+ instSrc[idx].dbl = val;
else if (width == 64)
instSrc[idx].dbl = val;
else
@@ -386,7 +386,14 @@
FloatReg
InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx, int width)
{
- return instSrc[idx].fp;
+ if (width == 32)
+ return (float)instSrc[idx].dbl;
+ else if (width == 64)
+ return instSrc[idx].dbl;
+ else {
+ panic("Unsupported Floating Point Width!");
+ return 0;
+ }
}
@@ -417,8 +424,10 @@
MiscReg
InOrderDynInst::readMiscRegOperandNoEffect(const StaticInst *si, int idx)
{
- int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
- return cpu->readMiscRegNoEffect(reg, this->threadNumber);
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Misc. Reg Source Value %i"
+ " read as %#x.\n", threadNumber, seqNum, idx,
+ instSrc[idx].integer);
+ return instSrc[idx].integer;
}
/** Reads a misc. register, including any side-effects the read
@@ -427,20 +436,23 @@
MiscReg
InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
{
- int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
- return this->cpu->readMiscReg(reg, this->threadNumber);
+ // For In-Order, the side-effect of reading a register happens
+ // when explicitly executing a "ReadSrc" command. This simply returns
+ // a value.
+ return readMiscRegOperandNoEffect(si, idx);
}
/** Sets a misc. register. */
void
-InOrderDynInst::setMiscRegOperandNoEffect(const StaticInst * si, int idx,
const MiscReg &val)
+InOrderDynInst::setMiscRegOperandNoEffect(const StaticInst * si, int idx,
+ const MiscReg &val)
{
- instResult[si->destRegIdx(idx)].val.integer = val;
- instResult[si->destRegIdx(idx)].tick = curTick;
+ instResult[idx].type = Integer;
+ instResult[idx].val.integer = val;
+ instResult[idx].tick = curTick;
- this->cpu->setMiscRegNoEffect(
- si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
- val, this->threadNumber);
+ DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Misc Reg. Operand %i "
+ "being set to %#x.\n", threadNumber, seqNum, idx, val);
}
/** Sets a misc. register, including any side-effects the write
@@ -450,12 +462,10 @@
InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
const MiscReg &val)
{
- instResult[si->destRegIdx(idx)].val.integer = val;
- instResult[si->destRegIdx(idx)].tick = curTick;
-
- this->cpu->setMiscReg(
- si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
- val, this->threadNumber);
+ // For In-Order, the side-effect of setting a register happens
+ // when explicitly writing back the register value. This
+ // simply maintains the operand value.
+ setMiscRegOperandNoEffect(si, idx, val);
}
MiscReg
@@ -480,6 +490,7 @@
void
InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
{
+ instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].tick = curTick;
}
@@ -488,12 +499,15 @@
void
InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg
val, int width)
{
- if (width == 32)
- instResult[idx].val.fp = val;
- else if (width == 64)
+ if (width == 32) {
+ instResult[idx].val.dbl = (float)val;
+ instResult[idx].type = Float;
+ } else if (width == 64) {
instResult[idx].val.dbl = val;
- else
+ instResult[idx].type = Double;
+ } else {
panic("Unsupported Floating Point Width!");
+ }
instResult[idx].tick = curTick;
}
@@ -503,6 +517,11 @@
InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
FloatRegBits val, int width)
{
+ if (width == 32)
+ instResult[idx].type = Float;
+ else if (width == 64)
+ instResult[idx].type = Double;
+
instResult[idx].val.integer = val;
instResult[idx].tick = curTick;
}
diff -r 19fedb1e5ded -r f51edf04e4a1 src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh Tue May 12 15:01:14 2009 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.hh Tue May 12 15:01:14 2009 -0400
@@ -226,14 +226,27 @@
/** An instruction src/dest has to be one of these types */
union InstValue {
uint64_t integer;
- float fp;
double dbl;
};
+ //@TODO: Naming Convention for Enums?
+ enum ResultType {
+ None,
+ Integer,
+ Float,
+ Double
+ };
+
+
/** Result of an instruction execution */
struct InstResult {
+ ResultType type;
InstValue val;
Tick tick;
+
+ InstResult()
+ : type(None), tick(0)
+ {}
};
/** The source of the instruction; assumes for now that there's only one
@@ -315,6 +328,9 @@
// BASE INSTRUCTION INFORMATION.
//
////////////////////////////////////////////////////////////
+ std::string instName() { return staticInst->getName(); }
+
+
void setMachInst(ExtMachInst inst);
/** Sets the StaticInst. */
@@ -827,9 +843,31 @@
MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
/** Returns the result value instruction. */
- uint64_t readIntResult(int idx) { return instResult[idx].val.integer; }
- float readFloatResult(int idx) { return instResult[idx].val.fp; }
- double readDoubleResult(int idx) { return instResult[idx].val.dbl; }
+ ResultType resultType(int idx)
+ {
+ return instResult[idx].type;
+ }
+
+ uint64_t readIntResult(int idx)
+ {
+ return instResult[idx].val.integer;
+ }
+
+ /** Depending on type, return Float or Double */
+ double readFloatResult(int idx)
+ {
+ //assert(instResult[idx].type != Integer && instResult[idx].type !=
None);
+ //@todo: TypeCast FLOAT onto DOUBLE instead of separate value
+ return (instResult[idx].type == Float) ?
+ (float) instResult[idx].val.dbl : instResult[idx].val.dbl;
+ }
+
+ double readDoubleResult(int idx)
+ {
+ assert(instResult[idx].type == Double);
+ return instResult[idx].val.dbl;
+ }
+
Tick readResultTime(int idx) { return instResult[idx].tick; }
uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }
diff -r 19fedb1e5ded -r f51edf04e4a1 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Tue May 12 15:01:14 2009 -0400
+++ b/src/cpu/inorder/resources/cache_unit.cc Tue May 12 15:01:14 2009 -0400
@@ -483,6 +483,9 @@
DPRINTF(InOrderCachePort,
"[tid:%u]: [sn:%i]: Data loaded was: %08p\n",
tid, inst->seqNum, inst->readIntResult(0));
+ DPRINTF(InOrderCachePort,
+ "[tid:%u]: [sn:%i]: FP Data loaded was: %08p\n",
+ tid, inst->seqNum, inst->readFloatResult(0));
} else if(inst->isStore()) {
assert(cache_pkt->isWrite());
@@ -594,7 +597,7 @@
case 32:
return packet->get<uint32_t>();
- case 864:
+ case 64:
return packet->get<uint64_t>();
default:
diff -r 19fedb1e5ded -r f51edf04e4a1 src/cpu/inorder/resources/execution_unit.cc
--- a/src/cpu/inorder/resources/execution_unit.cc Tue May 12 15:01:14
2009 -0400
+++ b/src/cpu/inorder/resources/execution_unit.cc Tue May 12 15:01:14
2009 -0400
@@ -68,8 +68,8 @@
exec_req->fault = NoFault;
- DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%#x] .\n",
- tid, seq_num, inst->readPC());
+ DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%#x] %s.\n",
+ tid, seq_num, inst->readPC(), inst->instName());
switch (exec_req->cmd)
{
@@ -163,11 +163,9 @@
}
} else {
DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction
Correct.\n",
- inst->readTid(), seq_num,
inst->readIntResult(0));
+ inst->readTid(), seq_num);
}
- DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of
execution is 0x%x.\n",
- inst->readTid(), seq_num, inst->readIntResult(0));
exec_req->done();
} else {
warn("inst [sn:%i] had a %s fault", seq_num,
fault->name());
@@ -178,10 +176,13 @@
if (fault == NoFault) {
inst->setExecuted();
- exec_req->done();
DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of
execution is 0x%x.\n",
- inst->readTid(), seq_num, inst->readIntResult(0));
+ inst->readTid(), seq_num, (inst->resultType(0) ==
InOrderDynInst::Float) ?
+ inst->readFloatResult(0) : (inst->resultType(0) ==
InOrderDynInst::Double) ?
+ inst->readDoubleResult(0) :
inst->readIntResult(0));
+
+ exec_req->done();
} else {
warn("inst [sn:%i] had a %s fault", seq_num,
fault->name());
cpu->trap(fault, tid);
diff -r 19fedb1e5ded -r f51edf04e4a1 src/cpu/inorder/resources/use_def.cc
--- a/src/cpu/inorder/resources/use_def.cc Tue May 12 15:01:14 2009 -0400
+++ b/src/cpu/inorder/resources/use_def.cc Tue May 12 15:01:14 2009 -0400
@@ -119,28 +119,28 @@
{
int reg_idx = inst->_srcRegIdx[ud_idx];
- DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to read source
register idx %i.\n",
- tid, ud_idx);
+ DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to read source
register idx %i (reg #%i).\n",
+ tid, ud_idx, reg_idx);
// Ask register dependency map if it is OK to read from Arch. Reg.
File
if (regDepMap[tid]->canRead(reg_idx, inst)) {
// Read From Register File
if (inst->seqNum <= outReadSeqNum[tid]) {
if (reg_idx <= FP_Base_DepTag) {
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