changeset 9925b3e83e06 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9925b3e83e06
description:
inorder-mem: skeleton support for prefetch/writehints
diffstat:
11 files changed, 113 insertions(+), 48 deletions(-)
src/arch/alpha/isa/mem.isa | 18 +++------
src/arch/alpha/tlb.cc | 2 -
src/cpu/inorder/cpu.cc | 15 ++++++++
src/cpu/inorder/cpu.hh | 10 +++++
src/cpu/inorder/inorder_dyn_inst.cc | 4 +-
src/cpu/inorder/resource.hh | 7 +++
src/cpu/inorder/resources/agen_unit.cc | 35 ++++--------------
src/cpu/inorder/resources/cache_unit.cc | 58 +++++++++++++++++++++++++++----
src/cpu/inorder/resources/cache_unit.hh | 4 ++
src/cpu/inorder/resources/tlb_unit.cc | 4 +-
src/cpu/inorder/resources/tlb_unit.hh | 4 ++
diffs (truncated from 323 to 300 lines):
diff -r c947586b3d9e -r 9925b3e83e06 src/arch/alpha/isa/mem.isa
--- a/src/arch/alpha/isa/mem.isa Tue May 12 15:01:14 2009 -0400
+++ b/src/arch/alpha/isa/mem.isa Tue May 12 15:01:15 2009 -0400
@@ -164,14 +164,6 @@
int memAccSize(%(CPU_exec_context)s *xc);
}};
-def template MiscMemAccSize {{
- int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
- {
- panic("Misc instruction does not support split access method!");
- return 0;
- }
-}};
-
def template LoadStoreMemAccSize {{
int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
{
@@ -451,7 +443,8 @@
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- warn("Misc instruction does not support split access method!");
+ warn("initiateAcc undefined: Misc instruction does not support split "
+ "access method!");
return NoFault;
}
}};
@@ -462,7 +455,8 @@
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- warn("Misc instruction does not support split access method!");
+ warn("completeAcc undefined: Misc instruction does not support split "
+ "access method!");
return NoFault;
}
@@ -471,7 +465,9 @@
def template MiscMemAccSize {{
int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
{
- panic("Misc instruction does not support split access method!");
+ return (%(mem_acc_size)d / 8);
+ panic("memAccSize undefined: Misc instruction does not support split "
+ "access method!");
return 0;
}
}};
diff -r c947586b3d9e -r 9925b3e83e06 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Tue May 12 15:01:14 2009 -0400
+++ b/src/arch/alpha/tlb.cc Tue May 12 15:01:15 2009 -0400
@@ -452,7 +452,7 @@
* Check for alignment faults
*/
if (req->getVaddr() & (req->getSize() - 1)) {
- DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
+ DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
req->getSize());
uint64_t flags = write ? MM_STAT_WR_MASK : 0;
return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
diff -r c947586b3d9e -r 9925b3e83e06 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Tue May 12 15:01:14 2009 -0400
+++ b/src/cpu/inorder/cpu.cc Tue May 12 15:01:15 2009 -0400
@@ -1264,6 +1264,21 @@
return mem_res->doDataAccess(inst);
}
+void
+InOrderCPU::prefetch(DynInstPtr inst)
+{
+ Resource *mem_res = resPool->getResource(dataPortIdx);
+ return mem_res->prefetch(inst);
+}
+
+void
+InOrderCPU::writeHint(DynInstPtr inst)
+{
+ Resource *mem_res = resPool->getResource(dataPortIdx);
+ return mem_res->writeHint(inst);
+}
+
+
TheISA::TLB*
InOrderCPU::getITBPtr()
{
diff -r c947586b3d9e -r 9925b3e83e06 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Tue May 12 15:01:14 2009 -0400
+++ b/src/cpu/inorder/cpu.hh Tue May 12 15:01:15 2009 -0400
@@ -497,6 +497,16 @@
*/
Fault write(DynInstPtr inst);
+ /** Forwards an instruction prefetch to the appropriate data
+ * resource (indexes into Resource Pool thru "dataPortIdx")
+ */
+ void prefetch(DynInstPtr inst);
+
+ /** Forwards an instruction writeHint to the appropriate data
+ * resource (indexes into Resource Pool thru "dataPortIdx")
+ */
+ void writeHint(DynInstPtr inst);
+
/** Executes a syscall.*/
void syscall(int64_t callnum, int tid);
diff -r c947586b3d9e -r 9925b3e83e06 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Tue May 12 15:01:14 2009 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Tue May 12 15:01:15 2009 -0400
@@ -296,13 +296,13 @@
void
InOrderDynInst::prefetch(Addr addr, unsigned flags)
{
- panic("Prefetch Unimplemented\n");
+ cpu->prefetch(this);
}
void
InOrderDynInst::writeHint(Addr addr, int size, unsigned flags)
{
- panic("Write-Hint Unimplemented\n");
+ cpu->writeHint(this);
}
/**
diff -r c947586b3d9e -r 9925b3e83e06 src/cpu/inorder/resource.hh
--- a/src/cpu/inorder/resource.hh Tue May 12 15:01:14 2009 -0400
+++ b/src/cpu/inorder/resource.hh Tue May 12 15:01:15 2009 -0400
@@ -143,6 +143,13 @@
virtual Fault doDataAccess(DynInstPtr inst)
{ panic("doDataAccess undefined for %s", name()); return NoFault; }
+ virtual void prefetch(DynInstPtr inst)
+ { panic("prefetch undefined for %s", name()); }
+
+ virtual void writeHint(DynInstPtr inst)
+ { panic("doDataAccess undefined for %s", name()); }
+
+
/** Squash All Requests After This Seq Num */
virtual void squash(DynInstPtr inst, int stage_num, InstSeqNum
squash_seq_num, unsigned tid);
diff -r c947586b3d9e -r 9925b3e83e06 src/cpu/inorder/resources/agen_unit.cc
--- a/src/cpu/inorder/resources/agen_unit.cc Tue May 12 15:01:14 2009 -0400
+++ b/src/cpu/inorder/resources/agen_unit.cc Tue May 12 15:01:15 2009 -0400
@@ -55,35 +55,18 @@
// Load/Store Instruction
if (inst->isMemRef()) {
DPRINTF(InOrderAGEN, "[tid:%i] Generating Address for [sn:%i]
(%s).\n",
- tid, inst->seqNum, inst->staticInst->getName());
+ tid, inst->seqNum, inst->staticInst->getName());
+ fault = inst->calcEA();
+ inst->setMemAddr(inst->getEA());
- // We are not handdling Prefetches quite yet
- if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
- panic("Prefetches arent handled yet.\n");
+ DPRINTF(InOrderAGEN, "[tid:%i] [sn:%i] Effective address
calculated to be: "
+ "%#x.\n", tid, inst->seqNum, inst->getEA());
+
+ if (fault == NoFault) {
+ agen_req->done();
} else {
- if (inst->isLoad()) {
- fault = inst->calcEA();
- inst->setMemAddr(inst->getEA());
- //inst->setExecuted();
-
- DPRINTF(InOrderAGEN, "[tid:%i] [sn:%i] Effective
address calculated to be: "
- "%#x.\n", tid, inst->seqNum, inst->getEA());
- } else if (inst->isStore()) {
- fault = inst->calcEA();
- inst->setMemAddr(inst->getEA());
-
- DPRINTF(InOrderAGEN, "[tid:%i] [sn:%i] Effective
address calculated to be: "
- "%#x.\n", tid, inst->seqNum, inst->getEA());
- } else {
- panic("Unexpected memory type!\n");
- }
-
- if (fault == NoFault) {
- agen_req->done();
- } else {
- fatal("%s encountered @ [sn:%i]",fault->name(),
seq_num);
- }
+ fatal("%s encountered while calculating address for
[sn:%i]",fault->name(), seq_num);
}
} else {
DPRINTF(InOrderAGEN, "[tid:] Ignoring non-memory instruction
[sn:%i].\n", tid, seq_num);
diff -r c947586b3d9e -r 9925b3e83e06 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Tue May 12 15:01:14 2009 -0400
+++ b/src/cpu/inorder/resources/cache_unit.cc Tue May 12 15:01:15 2009 -0400
@@ -230,11 +230,10 @@
DynInstPtr inst = cache_req->inst;
int tid;
+ int seq_num;
+
tid = inst->readTid();
- int seq_num;
seq_num = inst->seqNum;
- //int stage_num = cache_req->getStageNum();
-
cache_req->fault = NoFault;
switch (cache_req->cmd)
@@ -304,8 +303,13 @@
tid, name(), cache_req->inst->getMemAddr());
inst->setCurResSlot(slot_num);
- //inst->memAccess();
- inst->initiateAcc();
+
+ if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
+ inst->execute();
+ } else {
+ inst->initiateAcc();
+ }
+
break;
case CompleteReadData:
@@ -313,7 +317,10 @@
DPRINTF(InOrderCachePort,
"[tid:%i]: [sn:%i]: Trying to Complete Data Access\n",
tid, inst->seqNum);
- if (cache_req->isMemAccComplete()) {
+
+ if (cache_req->isMemAccComplete() ||
+ inst->isDataPrefetch() ||
+ inst->isInstPrefetch()) {
cache_req->done();
} else {
DPRINTF(InOrderStall, "STALL: [tid:%i]: Data miss from %08p\n",
@@ -327,6 +334,45 @@
}
}
+void
+CacheUnit::prefetch(DynInstPtr inst)
+{
+ warn_once("Prefetching currently unimplemented");
+
+ CacheReqPtr cache_req
+ = dynamic_cast<CacheReqPtr>(reqMap[inst->getCurResSlot()]);
+ assert(cache_req);
+
+ // Clean-Up cache resource request so
+ // other memory insts. can use them
+ cache_req->setCompleted();
+ cacheStatus = cacheAccessComplete;
+ cacheBlocked = false;
+ cache_req->setMemAccPending(false);
+ cache_req->setMemAccCompleted();
+ inst->unsetMemAddr();
+}
+
+
+void
+CacheUnit::writeHint(DynInstPtr inst)
+{
+ warn_once("Write Hints currently unimplemented");
+
+ CacheReqPtr cache_req
+ = dynamic_cast<CacheReqPtr>(reqMap[inst->getCurResSlot()]);
+ assert(cache_req);
+
+ // Clean-Up cache resource request so
+ // other memory insts. can use them
+ cache_req->setCompleted();
+ cacheStatus = cacheAccessComplete;
+ cacheBlocked = false;
+ cache_req->setMemAccPending(false);
+ cache_req->setMemAccCompleted();
+ inst->unsetMemAddr();
+}
+
Fault
CacheUnit::doDataAccess(DynInstPtr inst)
{
diff -r c947586b3d9e -r 9925b3e83e06 src/cpu/inorder/resources/cache_unit.hh
--- a/src/cpu/inorder/resources/cache_unit.hh Tue May 12 15:01:14 2009 -0400
+++ b/src/cpu/inorder/resources/cache_unit.hh Tue May 12 15:01:15 2009 -0400
@@ -172,6 +172,10 @@
*/
Fault doDataAccess(DynInstPtr inst);
+ void prefetch(DynInstPtr inst);
+
+ void writeHint(DynInstPtr inst);
+
uint64_t getMemData(Packet *packet);
protected:
diff -r c947586b3d9e -r 9925b3e83e06 src/cpu/inorder/resources/tlb_unit.cc
--- a/src/cpu/inorder/resources/tlb_unit.cc Tue May 12 15:01:14 2009 -0400
+++ b/src/cpu/inorder/resources/tlb_unit.cc Tue May 12 15:01:15 2009 -0400
@@ -158,8 +158,8 @@
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