changeset 761e0f61a167 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=761e0f61a167
description:
inorder-mem: clean up allocation/deletion of requests/packets
* * *
diffstat:
5 files changed, 38 insertions(+), 18 deletions(-)
src/cpu/inorder/inorder_dyn_inst.cc | 14 +++++++++++---
src/cpu/inorder/inorder_dyn_inst.hh | 3 ++-
src/cpu/inorder/resources/cache_unit.cc | 7 +++++++
src/cpu/inorder/resources/cache_unit.hh | 11 +++++++----
src/cpu/inorder/resources/tlb_unit.hh | 21 +++++++++++----------
diffs (146 lines):
diff -r 9925b3e83e06 -r 761e0f61a167 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Tue May 12 15:01:15 2009 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Tue May 12 15:01:15 2009 -0400
@@ -108,7 +108,9 @@
void
InOrderDynInst::initVars()
{
- req = NULL;
+ fetchMemReq = NULL;
+ dataMemReq = NULL;
+
effAddr = 0;
physEffAddr = 0;
@@ -170,8 +172,14 @@
InOrderDynInst::~InOrderDynInst()
{
- if (req) {
- delete req;
+ if (fetchMemReq != 0x0) {
+ delete fetchMemReq;
+ fetchMemReq = NULL;
+ }
+
+ if (dataMemReq != 0x0) {
+ delete dataMemReq;
+ dataMemReq = NULL;
}
if (traceData) {
diff -r 9925b3e83e06 -r 761e0f61a167 src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh Tue May 12 15:01:15 2009 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.hh Tue May 12 15:01:15 2009 -0400
@@ -634,7 +634,8 @@
/** Read Effective Address from instruction & do memory access */
Fault memAccess();
- RequestPtr memReq;
+ RequestPtr fetchMemReq;
+ RequestPtr dataMemReq;
bool memAddrReady;
diff -r 9925b3e83e06 -r 761e0f61a167 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Tue May 12 15:01:15 2009 -0400
+++ b/src/cpu/inorder/resources/cache_unit.cc Tue May 12 15:01:15 2009 -0400
@@ -252,6 +252,8 @@
break;
case CompleteFetch:
+ // @TODO: MOVE Functionality of handling fetched data into 'fetch unit'
+ // let cache-unit just be responsible for transferring data.
if (cache_req->isMemAccComplete()) {
DPRINTF(InOrderCachePort,
"[tid:%i]: Completing Fetch Access for [sn:%i]\n",
@@ -284,6 +286,8 @@
inst->traceData->setPC(inst->readPC());
}
+ delete cache_req->dataPkt;
+
cache_req->done();
} else {
DPRINTF(InOrderCachePort,
@@ -481,6 +485,7 @@
cache_pkt->cacheReq->getInst()->seqNum);
cache_pkt->cacheReq->done();
+ delete cache_pkt;
return;
}
@@ -543,6 +548,8 @@
getMemData(cache_pkt));
}
+
+ delete cache_pkt;
}
cache_req->setMemAccPending(false);
diff -r 9925b3e83e06 -r 761e0f61a167 src/cpu/inorder/resources/cache_unit.hh
--- a/src/cpu/inorder/resources/cache_unit.hh Tue May 12 15:01:15 2009 -0400
+++ b/src/cpu/inorder/resources/cache_unit.hh Tue May 12 15:01:15 2009 -0400
@@ -246,7 +246,13 @@
: ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd),
pktCmd(pkt_cmd), memAccComplete(false), memAccPending(false)
{
- memReq = inst->memReq;
+ if (cmd == CacheUnit::InitiateFetch ||
+ cmd == CacheUnit::CompleteFetch ||
+ cmd == CacheUnit::Fetch) {
+ memReq = inst->fetchMemReq;
+ } else {
+ memReq = inst->dataMemReq;
+ }
reqData = new uint8_t[req_size];
retryPkt = NULL;
@@ -273,9 +279,6 @@
delete retryPkt;
}
#endif
-
- if (memReq)
- delete memReq;
}
virtual PacketDataPtr getData()
diff -r 9925b3e83e06 -r 761e0f61a167 src/cpu/inorder/resources/tlb_unit.hh
--- a/src/cpu/inorder/resources/tlb_unit.hh Tue May 12 15:01:15 2009 -0400
+++ b/src/cpu/inorder/resources/tlb_unit.hh Tue May 12 15:01:15 2009 -0400
@@ -106,21 +106,22 @@
aligned_addr = inst->getMemAddr();
req_size = sizeof(TheISA::MachInst);
flags = 0;
+ inst->fetchMemReq = new Request(inst->readTid(), aligned_addr,
req_size,
+ flags, inst->readPC(),
res->cpu->readCpuId(), inst->readTid());
+ memReq = inst->fetchMemReq;
} else {
aligned_addr = inst->getMemAddr();;
req_size = inst->getMemAccSize();
flags = inst->getMemFlags();
+
+ if (req_size == 0 && (inst->isDataPrefetch() ||
inst->isInstPrefetch())) {
+ req_size = 8;
+ }
+
+ inst->dataMemReq = new Request(inst->readTid(), aligned_addr,
req_size,
+ flags, inst->readPC(),
res->cpu->readCpuId(), inst->readTid());
+ memReq = inst->dataMemReq;
}
-
- if (req_size == 0 && (inst->isDataPrefetch() ||
inst->isInstPrefetch())) {
- req_size = 8;
- }
-
- // @TODO: Add Vaddr & Paddr functions
- inst->memReq = new Request(inst->readTid(), aligned_addr, req_size,
- flags, inst->readPC(),
res->cpu->readCpuId(), inst->readTid());
-
- memReq = inst->memReq;
}
RequestPtr memReq;
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
