changeset a5334d8c6683 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a5334d8c6683
description:
inorder-stc: update interface to handle store conditionals
diffstat:
6 files changed, 29 insertions(+), 21 deletions(-)
src/cpu/inorder/cpu.cc | 4 +--
src/cpu/inorder/cpu.hh | 2 -
src/cpu/inorder/inorder_dyn_inst.cc | 2 -
src/cpu/inorder/resource.hh | 2 -
src/cpu/inorder/resources/cache_unit.cc | 36 ++++++++++++++++++-------------
src/cpu/inorder/resources/cache_unit.hh | 4 ++-
diffs (169 lines):
diff -r bfb323a1c559 -r a5334d8c6683 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Tue May 12 15:01:15 2009 -0400
+++ b/src/cpu/inorder/cpu.cc Tue May 12 15:01:15 2009 -0400
@@ -1258,10 +1258,10 @@
}
Fault
-InOrderCPU::write(DynInstPtr inst)
+InOrderCPU::write(DynInstPtr inst, uint64_t *res)
{
Resource *mem_res = resPool->getResource(dataPortIdx);
- return mem_res->doDataAccess(inst);
+ return mem_res->doDataAccess(inst, res);
}
void
diff -r bfb323a1c559 -r a5334d8c6683 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Tue May 12 15:01:15 2009 -0400
+++ b/src/cpu/inorder/cpu.hh Tue May 12 15:01:15 2009 -0400
@@ -495,7 +495,7 @@
/** Forwards an instruction write. to the appropriate data
* resource (indexes into Resource Pool thru "dataPortIdx")
*/
- Fault write(DynInstPtr inst);
+ Fault write(DynInstPtr inst, uint64_t *res = NULL);
/** Forwards an instruction prefetch to the appropriate data
* resource (indexes into Resource Pool thru "dataPortIdx")
diff -r bfb323a1c559 -r a5334d8c6683 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Tue May 12 15:01:15 2009 -0400
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Tue May 12 15:01:15 2009 -0400
@@ -657,7 +657,7 @@
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting store data to %#x.\n",
threadNumber, seqNum, memData);
- return cpu->write(this);
+ return cpu->write(this, res);
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
diff -r bfb323a1c559 -r a5334d8c6683 src/cpu/inorder/resource.hh
--- a/src/cpu/inorder/resource.hh Tue May 12 15:01:15 2009 -0400
+++ b/src/cpu/inorder/resource.hh Tue May 12 15:01:15 2009 -0400
@@ -140,7 +140,7 @@
* if instruction is actually in resource before
* trying to do access.Needs to be defined for derived units.
*/
- virtual Fault doDataAccess(DynInstPtr inst)
+ virtual Fault doDataAccess(DynInstPtr inst, uint64_t *res=NULL)
{ panic("doDataAccess undefined for %s", name()); return NoFault; }
virtual void prefetch(DynInstPtr inst)
diff -r bfb323a1c559 -r a5334d8c6683 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Tue May 12 15:01:15 2009 -0400
+++ b/src/cpu/inorder/resources/cache_unit.cc Tue May 12 15:01:15 2009 -0400
@@ -175,7 +175,7 @@
inst->readTid(), req_size, inst->seqNum, inst->getMemAddr());
} else if (sched_entry->cmd == InitiateFetch){
pkt_cmd = MemCmd::ReadReq;
- req_size = sizeof(MachInst); //@TODO: mips16e
+ req_size = sizeof(MachInst);
DPRINTF(InOrderCachePort,
"[tid:%i]: %i byte Fetch request from [sn:%i] for addr %08p\n",
@@ -356,7 +356,7 @@
}
Fault
-CacheUnit::doDataAccess(DynInstPtr inst)
+CacheUnit::doDataAccess(DynInstPtr inst, uint64_t *write_res)
{
Fault fault = NoFault;
int tid = 0;
@@ -367,6 +367,17 @@
= dynamic_cast<CacheReqPtr>(reqMap[inst->getCurResSlot()]);
assert(cache_req);
+ // Check for LL/SC and if so change command
+ if (cache_req->memReq->isLLSC() && cache_req->pktCmd == MemCmd::ReadReq) {
+ cache_req->pktCmd = MemCmd::LoadLockedReq;
+ }
+
+ if (cache_req->pktCmd == MemCmd::WriteReq) {
+ cache_req->pktCmd =
+ cache_req->memReq->isSwap() ? MemCmd::SwapReq :
+ (cache_req->memReq->isLLSC() ? MemCmd::StoreCondReq :
MemCmd::WriteReq);
+ }
+
cache_req->dataPkt = new CacheReqPacket(cache_req, cache_req->pktCmd,
Packet::Broadcast);
@@ -374,6 +385,11 @@
cache_req->dataPkt->dataStatic(cache_req->reqData);
} else if (cache_req->dataPkt->isWrite()) {
cache_req->dataPkt->dataStatic(&cache_req->inst->storeData);
+
+ if (cache_req->memReq->isCondSwap()) {
+ assert(write_res);
+ cache_req->memReq->setExtraData(*write_res);
+ }
}
cache_req->dataPkt->time = curTick;
@@ -382,7 +398,7 @@
Request *memReq = cache_req->dataPkt->req;
- if (cache_req->dataPkt->isWrite() && memReq->isLLSC()) {
+ if (cache_req->dataPkt->isWrite() && cache_req->memReq->isLLSC()) {
assert(cache_req->inst->isStoreConditional());
DPRINTF(InOrderCachePort, "Evaluating Store Conditional access\n");
do_access = TheISA::handleLockedWrite(cpu, memReq);
@@ -392,11 +408,7 @@
"[tid:%i] [sn:%i] attempting to access cache\n",
tid, inst->seqNum);
- //@TODO: If you want to ignore failed store conditional accesses, then
- // enable this. However, this might skew memory stats because
- // the failed store conditional access will get ignored.
- // - Remove optionality here ...
- if (1/*do_access*/) {
+ if (do_access) {
if (!cachePort->sendTiming(cache_req->dataPkt)) {
DPRINTF(InOrderCachePort,
"[tid:%i] [sn:%i] is waiting to retry request\n",
@@ -431,13 +443,7 @@
"[tid:%i]: T%i Ignoring Failed Store Conditional Access\n",
tid, tid);
- cache_req->dataPkt->req->setExtraData(0);
-
processCacheCompletion(cache_req->dataPkt);
-
- // Automatically set these since we ignored the memory access
- //cache_req->setMemAccPending(false);
- //cache_req->setMemAccCompleted();
} else {
// Make cache request again since access due to
// inability to access
@@ -535,7 +541,7 @@
TheISA::handleLockedRead(cpu, cache_pkt->req);
}
- // @TODO: Hardcoded to for load instructions. Assumes that
+ // @NOTE: Hardcoded to for load instructions. Assumes that
// the dest. idx 0 is always where the data is loaded to.
DPRINTF(InOrderCachePort,
"[tid:%u]: [sn:%i]: Data loaded was: %08p\n",
diff -r bfb323a1c559 -r a5334d8c6683 src/cpu/inorder/resources/cache_unit.hh
--- a/src/cpu/inorder/resources/cache_unit.hh Tue May 12 15:01:15 2009 -0400
+++ b/src/cpu/inorder/resources/cache_unit.hh Tue May 12 15:01:15 2009 -0400
@@ -162,7 +162,7 @@
/** Read/Write on behalf of an instruction.
* curResSlot needs to be a valid value in instruction.
*/
- Fault doDataAccess(DynInstPtr inst);
+ Fault doDataAccess(DynInstPtr inst, uint64_t *write_result=NULL);
void prefetch(DynInstPtr inst);
@@ -245,6 +245,8 @@
memReq = inst->dataMemReq;
}
+ //@ Only matters for Fetch / Read requests
+ // Don't allocate for Writes!
reqData = new uint8_t[req_size];
retryPkt = NULL;
}
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