changeset 55e837d741fa in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=55e837d741fa
description:
inorder-faults: ignore unalign translation faults for prefetches
diffstat:
1 file changed, 9 insertions(+), 1 deletion(-)
src/cpu/inorder/resources/tlb_unit.cc | 10 +++++++++-
diffs (26 lines):
diff -r a5334d8c6683 -r 55e837d741fa src/cpu/inorder/resources/tlb_unit.cc
--- a/src/cpu/inorder/resources/tlb_unit.cc Tue May 12 15:01:15 2009 -0400
+++ b/src/cpu/inorder/resources/tlb_unit.cc Tue May 12 15:01:16 2009 -0400
@@ -161,13 +161,21 @@
"addr:%08p for [sn:%i] %s.\n", tid,
tlb_req->fault->name(),
tlb_req->memReq->getVaddr(), seq_num,
inst->instName());
+ if (inst->isDataPrefetch()) {
+ DPRINTF(InOrderTLB, "Ignoring %s fault for data
prefetch\n",
+ tlb_req->fault->name());
+
+ tlb_req->fault = NoFault;
+
+ tlb_req->done();
+ } else {
cpu->pipelineStage[stage_num]->setResStall(tlb_req, tid);
tlbBlocked[tid] = true;
scheduleEvent(slot_idx, 1);
// Let CPU handle the fault
cpu->trap(tlb_req->fault, tid);
-
+ }
} else {
DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p
translated "
"to phys. addr:%08p.\n", tid, seq_num,
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