changeset 2078ba7cefe4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2078ba7cefe4
description:
inorder-regress: add hello world
diffstat:
5 files changed, 510 insertions(+), 1 deletion(-)
tests/SConscript | 3
tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini | 223 ++++++++
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr | 3
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout | 17
tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt | 265 ++++++++++
diffs (truncated from 537 to 300 lines):
diff -r 50668b97c086 -r 2078ba7cefe4 tests/SConscript
--- a/tests/SConscript Tue May 12 15:01:16 2009 -0400
+++ b/tests/SConscript Tue May 12 15:01:16 2009 -0400
@@ -263,7 +263,8 @@
else:
configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
- 'simple-atomic-mp', 'simple-timing-mp', 'o3-timing-mp']
+ 'simple-atomic-mp', 'simple-timing-mp', 'o3-timing-mp',
+ 'inorder-timing']
if env['RUBY']:
# Hack for Ruby
diff -r 50668b97c086 -r 2078ba7cefe4
tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini Tue May
12 15:01:16 2009 -0400
@@ -0,0 +1,223 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=InOrderCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+activity=0
+cachePorts=2
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+cpu_id=0
+dataMemPort=dcache_port
+defer_registration=false
+div16Latency=1
+div16RepeatRate=1
+div24Latency=1
+div24RepeatRate=1
+div32Latency=1
+div32RepeatRate=1
+div8Latency=1
+div8RepeatRate=1
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchMemPort=icache_port
+functionTrace=false
+functionTraceStart=0
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+memBlockSize=64
+multLatency=1
+multRepeatRate=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+stageTracing=false
+stageWidth=1
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=10000
+max_miss_count=0
+mshrs=10
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side
system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+responder_set=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff -r 50668b97c086 -r 2078ba7cefe4
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr Tue May
12 15:01:16 2009 -0400
@@ -0,0 +1,3 @@
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
diff -r 50668b97c086 -r 2078ba7cefe4
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout Tue May
12 15:01:16 2009 -0400
@@ -0,0 +1,17 @@
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled May 12 2009 11:18:39
+M5 revision 21550d38f156 6195 default qtip tip inorder-hello-regress
+M5 started May 12 2009 11:18:40
+M5 executing on zooks
+command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re
tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 31646000 because target called exit()
diff -r 50668b97c086 -r 2078ba7cefe4
tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt Tue May
12 15:01:16 2009 -0400
@@ -0,0 +1,265 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 23793 #
Simulator instruction rate (inst/s)
+host_mem_usage 152032 #
Number of bytes of host memory used
+host_seconds 0.27 #
Real time elapsed on the host
+host_tick_rate 117464960 #
Simulator tick rate (ticks/s)
+sim_freq 1000000000000 #
Frequency of simulated ticks
+sim_insts 6404 #
Number of instructions simulated
+sim_seconds 0.000032 #
Number of seconds simulated
+sim_ticks 31646000 #
Number of ticks simulated
+system.cpu.AGEN-Unit.instReqsProcessed 2050 #
Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.instReqsProcessed 6405
# Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.predictedNotTaken 909
# Number of Branches Predicted As Not Taken (False).
+system.cpu.Branch-Predictor.predictedTaken 142
# Number of Branches Predicted As Taken (True).
+system.cpu.Decode-Unit.instReqsProcessed 6405 #
Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.instReqsProcessed 4354
# Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.predictedNotTakenIncorrect 607
# Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.Execution-Unit.predictedTakenIncorrect 124
# Number of Branches Incorrectly Predicted As Taken.
+system.cpu.Fetch-Buffer-T0.instReqsProcessed 0
# Number of Instructions Requests that completed in this resource.
+system.cpu.Fetch-Buffer-T0.instsBypassed 0 #
Number of Instructions Bypassed.
+system.cpu.Fetch-Buffer-T1.instReqsProcessed 0
# Number of Instructions Requests that completed in this resource.
+system.cpu.Fetch-Buffer-T1.instsBypassed 0 #
Number of Instructions Bypassed.
+system.cpu.Fetch-Seq-Unit.instReqsProcessed 13560
# Number of Instructions Requests that completed in this resource.
+system.cpu.Graduation-Unit.instReqsProcessed 6404
# Number of Instructions Requests that completed in this resource.
+system.cpu.Mult-Div-Unit.divInstReqsProcessed 0
# Number of Divide Requests Processed.
+system.cpu.Mult-Div-Unit.instReqsProcessed 2
# Number of Instructions Requests that completed in this resource.
+system.cpu.Mult-Div-Unit.multInstReqsProcessed 1
# Number of Multiply Requests Processed.
+system.cpu.RegFile-Manager.instReqsProcessed 12884
# Number of Instructions Requests that completed in this resource.
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