changeset 6cd5f0282d8a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6cd5f0282d8a
description:
inorder-tlb-cunit: merge the TLB as implicit to any memory access
TLBUnit no longer used and we also get rid of memAccSize and
memAccFlags functions added to ISA and StaticInst
since TLB is not a separate resource to acquire. Instead, TLB access is
done before any read/write to memory
and the result is checked before it's sent out to memory.
* * *
diffstat:
16 files changed, 516 insertions(+), 195 deletions(-)
src/arch/alpha/isa/mem.isa | 36 --
src/cpu/SConscript | 2
src/cpu/inorder/SConscript | 1
src/cpu/inorder/cpu.cc | 164 +++++++++++--
src/cpu/inorder/cpu.hh | 7
src/cpu/inorder/inorder_dyn_inst.cc | 4
src/cpu/inorder/inorder_dyn_inst.hh | 4
src/cpu/inorder/pipeline_traits.cc | 6
src/cpu/inorder/pipeline_traits.hh | 2
src/cpu/inorder/resource.hh | 7
src/cpu/inorder/resource_pool.cc | 7
src/cpu/inorder/resources/cache_unit.cc | 373 +++++++++++++++++++++++++++----
src/cpu/inorder/resources/cache_unit.hh | 85 +++----
src/cpu/inorder/resources/tlb_unit.hh | 4
src/cpu/static_inst.cc | 7
src/cpu/static_inst.hh | 2
diffs (truncated from 1149 to 300 lines):
diff -r 2afc0eae6099 -r 6cd5f0282d8a src/arch/alpha/isa/mem.isa
--- a/src/arch/alpha/isa/mem.isa Tue May 12 15:01:16 2009 -0400
+++ b/src/arch/alpha/isa/mem.isa Tue May 12 15:01:16 2009 -0400
@@ -53,10 +53,6 @@
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-
- public:
-
- Request::Flags memAccFlags() { return memAccessFlags; }
};
/**
@@ -140,8 +136,6 @@
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
-
- %(MemAccSizeDeclare)s
};
}};
@@ -160,19 +154,6 @@
Trace::InstRecord *) const;
}};
-def template MemAccSizeDeclare {{
- int memAccSize(%(CPU_exec_context)s *xc);
-}};
-
-def template LoadStoreMemAccSize {{
- int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
- {
- // Return the memory access size in bytes
- return (%(mem_acc_size)d / 8);
- }
-}};
-
-
def template LoadStoreConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
@@ -462,15 +443,6 @@
}
}};
-def template MiscMemAccSize {{
- int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
- {
- return (%(mem_acc_size)d / 8);
- panic("memAccSize undefined: Misc instruction does not support split "
- "access method!");
- return 0;
- }
-}};
// load instructions use Ra as dest, so check for
// Ra == 31 to detect nops
@@ -541,11 +513,6 @@
initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
- if (exec_template_base == 'Load' or exec_template_base == 'Store'):
- memAccSizeTemplate = eval('LoadStoreMemAccSize')
- else:
- memAccSizeTemplate = eval('MiscMemAccSize')
-
# (header_output, decoder_output, decode_block, exec_output)
return (LoadStoreDeclare.subst(iop),
LoadStoreConstructor.subst(iop),
@@ -553,8 +520,7 @@
fullExecTemplate.subst(iop)
+ EACompExecute.subst(iop)
+ initiateAccTemplate.subst(iop)
- + completeAccTemplate.subst(iop)
- + memAccSizeTemplate.subst(memacc_iop))
+ + completeAccTemplate.subst(iop))
}};
def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
diff -r 2afc0eae6099 -r 6cd5f0282d8a src/cpu/SConscript
--- a/src/cpu/SConscript Tue May 12 15:01:16 2009 -0400
+++ b/src/cpu/SConscript Tue May 12 15:01:16 2009 -0400
@@ -56,8 +56,6 @@
virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
Trace::InstRecord *traceData) const
{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
-virtual int memAccSize(%(type)s *xc)
-{ panic("memAccSize not defined!"); M5_DUMMY_RETURN };
'''
mem_ini_sig_template = '''
diff -r 2afc0eae6099 -r 6cd5f0282d8a src/cpu/inorder/SConscript
--- a/src/cpu/inorder/SConscript Tue May 12 15:01:16 2009 -0400
+++ b/src/cpu/inorder/SConscript Tue May 12 15:01:16 2009 -0400
@@ -75,7 +75,6 @@
Source('resources/decode_unit.cc')
Source('resources/inst_buffer.cc')
Source('resources/graduation_unit.cc')
- Source('resources/tlb_unit.cc')
Source('resources/fetch_seq_unit.cc')
Source('resources/mult_div_unit.cc')
Source('resource_pool.cc')
diff -r 2afc0eae6099 -r 6cd5f0282d8a src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Tue May 12 15:01:16 2009 -0400
+++ b/src/cpu/inorder/cpu.cc Tue May 12 15:01:16 2009 -0400
@@ -204,18 +204,6 @@
fatal("Unable to find port for data.\n");
}
-
- // Hard-Code Bindings to ITB & DTB
- itbIdx = resPool->getResIdx(name() + "." + "I-TLB");
- if (itbIdx == 0) {
- fatal("Unable to find ITB resource.\n");
- }
-
- dtbIdx = resPool->getResIdx(name() + "." + "D-TLB");
- if (dtbIdx == 0) {
- fatal("Unable to find DTB resource.\n");
- }
-
for (int i = 0; i < numThreads; ++i) {
if (i < params->workload.size()) {
DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
@@ -486,6 +474,7 @@
void
InOrderCPU::trap(Fault fault, unsigned tid, int delay)
{
+ //@ Squash Pipeline during TRAP
scheduleCpuEvent(Trap, fault, tid, 0/*vpe*/, delay);
}
@@ -502,7 +491,7 @@
CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, vpe);
if (delay >= 0) {
- DPRINTF(InOrderCPU, "Scheduling CPU Event Type #%s for cycle %i.\n",
+ DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i.\n",
eventNames[c_event], curTick + delay);
mainEventQueue.schedule(cpu_event,curTick + delay);
} else {
@@ -1266,20 +1255,6 @@
nonSpecInstActive[tid] = false;
}
-Fault
-InOrderCPU::read(DynInstPtr inst)
-{
- Resource *mem_res = resPool->getResource(dataPortIdx);
- return mem_res->doDataAccess(inst);
-}
-
-Fault
-InOrderCPU::write(DynInstPtr inst, uint64_t *res)
-{
- Resource *mem_res = resPool->getResource(dataPortIdx);
- return mem_res->doDataAccess(inst, res);
-}
-
void
InOrderCPU::prefetch(DynInstPtr inst)
{
@@ -1298,7 +1273,8 @@
TheISA::TLB*
InOrderCPU::getITBPtr()
{
- TLBUnit *itb_res = dynamic_cast<TLBUnit*>(resPool->getResource(itbIdx));
+ CacheUnit *itb_res =
+ dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
return itb_res->tlb();
}
@@ -1306,6 +1282,136 @@
TheISA::TLB*
InOrderCPU::getDTBPtr()
{
- TLBUnit *dtb_res = dynamic_cast<TLBUnit*>(resPool->getResource(dtbIdx));
+ CacheUnit *dtb_res =
+ dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
return dtb_res->tlb();
}
+
+template <class T>
+Fault
+InOrderCPU::read(DynInstPtr inst, Addr addr, T &data, unsigned flags)
+{
+ //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
+ // you want to run w/out caches?
+ CacheUnit *cache_res =
dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
+
+ return cache_res->read(inst, addr, data, flags);
+}
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+
+template
+Fault
+InOrderCPU::read(DynInstPtr inst, Addr addr, Twin32_t &data, unsigned flags);
+
+template
+Fault
+InOrderCPU::read(DynInstPtr inst, Addr addr, Twin64_t &data, unsigned flags);
+
+template
+Fault
+InOrderCPU::read(DynInstPtr inst, Addr addr, uint64_t &data, unsigned flags);
+
+template
+Fault
+InOrderCPU::read(DynInstPtr inst, Addr addr, uint32_t &data, unsigned flags);
+
+template
+Fault
+InOrderCPU::read(DynInstPtr inst, Addr addr, uint16_t &data, unsigned flags);
+
+template
+Fault
+InOrderCPU::read(DynInstPtr inst, Addr addr, uint8_t &data, unsigned flags);
+
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+template<>
+Fault
+InOrderCPU::read(DynInstPtr inst, Addr addr, double &data, unsigned flags)
+{
+ return read(inst, addr, *(uint64_t*)&data, flags);
+}
+
+template<>
+Fault
+InOrderCPU::read(DynInstPtr inst, Addr addr, float &data, unsigned flags)
+{
+ return read(inst, addr, *(uint32_t*)&data, flags);
+}
+
+
+template<>
+Fault
+InOrderCPU::read(DynInstPtr inst, Addr addr, int32_t &data, unsigned flags)
+{
+ return read(inst, addr, (uint32_t&)data, flags);
+}
+
+template <class T>
+Fault
+InOrderCPU::write(DynInstPtr inst, T data, Addr addr, unsigned flags,
+ uint64_t *write_res)
+{
+ //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
+ // you want to run w/out caches?
+ CacheUnit *cache_res =
+ dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
+ return cache_res->write(inst, data, addr, flags, write_res);
+}
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+
+template
+Fault
+InOrderCPU::write(DynInstPtr inst, Twin32_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+InOrderCPU::write(DynInstPtr inst, Twin64_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+InOrderCPU::write(DynInstPtr inst, uint64_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+InOrderCPU::write(DynInstPtr inst, uint32_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+InOrderCPU::write(DynInstPtr inst, uint16_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+InOrderCPU::write(DynInstPtr inst, uint8_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+template<>
+Fault
+InOrderCPU::write(DynInstPtr inst, double data, Addr addr, unsigned flags,
uint64_t *res)
+{
+ return write(inst, *(uint64_t*)&data, addr, flags, res);
+}
+
+template<>
+Fault
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