changeset 17e7ab512377 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=17e7ab512377
description:
ARM: Add a cmpxchg implementation to the "comm page".
This implementation does what it's supposed to (I think), but it's not
atomic
and doesn't have memory barriers like the kernel's version.
diffstat:
1 file changed, 12 insertions(+)
src/arch/arm/linux/process.cc | 12 ++++++++++++
diffs (22 lines):
diff -r 014ae6da6c2a -r 17e7ab512377 src/arch/arm/linux/process.cc
--- a/src/arch/arm/linux/process.cc Tue Jun 09 23:39:07 2009 -0700
+++ b/src/arch/arm/linux/process.cc Tue Jun 09 23:41:03 2009 -0700
@@ -482,6 +482,18 @@
swiNeg1, sizeof(swiNeg1));
}
+ // This -should- be atomic, but I don't think all the support that we'd
+ // need is implemented. There should also be memory barriers around it.
+ uint8_t cmpxchg[] =
+ {
+ 0x00, 0x30, 0x92, 0xe5, //ldr r3, [r2]
+ 0x00, 0x30, 0x53, 0xe0, //subs r3, r3, r0
+ 0x00, 0x10, 0x92, 0x05, //streq r1, [r2]
+ 0x03, 0x00, 0xa0, 0xe1, //mov r0, r3
+ 0x0e, 0xf0, 0xa0, 0xe1 //usr_ret lr
+ };
+ tc->getMemPort()->writeBlob(commPage + 0x0fc0, cmpxchg, sizeof(cmpxchg));
+
uint8_t get_tls[] =
{
0x08, 0x00, 0x9f, 0xe5, //ldr r0, [pc, #(16 - 8)]
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