I'm moving ARM's R15/PC handling into the instructions themselves instead of the register file for a number of reasons. There are a number of difficulties associated with that, some of which I've dealt with and some I haven't. In both cases, life would be a lot easier if I had more explicit control over over the code that reads from and writes to the operands. I'd like to make %(op_rd)s and %(op_wb)s check if they're accessing R15 and read/write the PC instead. Instructions that know they're going to write the PC (ignoring predication) would be instructed/constructed to set the "branch" bit (or whatever it's called). That's actually one of the reasons the instructions need to know when they're going to modify the PC. Does anyone have a suggestion for how something like that might work? I have some ideas, but they involve fairly dramatic changes to how ISAs are defined. I'd like to avoid getting sucked into something like that right now if possible, although I wouldn't necessarily mind.
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