On Jun 29, 2009, at 7:28 PM, Jack Whitham wrote: > > Sounds reasonable. I thought about doing it this way, but wasn't sure > how to do it without major changes in decoder.isa. > > However - I've hit a related issue, that could also be solved by a > large > change to decoder.isa, but probably has a much better solution. > Consider a chain of conditional instructions: > cmp r0, #1 > cmpne r0, #2 > cmpne r0, #3 > Here, instructions 2 and 3 depend on their immediate predecessors. > Each > instruction generates a set of flags (Cpsr) which determines if the > next > instruction will execute or not. This limits the ILP available - O3 > cannot reorder or parallelise these instructions. Each uses input from > the previous instruction. > > The same situation incorrectly occurs when the instructions are *not* > conditional, e.g. > cmp r0, #1 > cmp r0, #2 > cmp r0, #3 > Even though the instructions are always executed, instructions 2 and 3 > *still* depend on their immediate predecessors because Cpsr is still > an input. The functionality is correct, but inefficient. Really, it > would seem best to flag these instructions as unconditional during > decode, > so that the Cpsr input could be ignored. That would permit O3 to > reorder > the instructions. > > Any suggestions on how to do this? A trick here is to make the condition code bits of the cpsr their own integer register and then when the cpsr is read merge the condition code bits with the rest of the register. That way renaming can solve the problem for you.
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