changeset 1cee707c1228 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1cee707c1228
description:
ARM: Pull some static code out of the isa desc and create miscregs.hh.
diffstat:
9 files changed, 138 insertions(+), 116 deletions(-)
src/arch/arm/isa/decoder.isa | 2
src/arch/arm/isa/formats/branch.isa | 4 -
src/arch/arm/isa/formats/fp.isa | 2
src/arch/arm/isa/formats/mem.isa | 24 ++++----
src/arch/arm/isa/formats/pred.isa | 92 +++-------------------------------
src/arch/arm/isa/operands.isa | 4 -
src/arch/arm/miscregs.hh | 83 ++++++++++++++++++++++++++++++
src/arch/arm/regfile/misc_regfile.hh | 16 -----
src/arch/arm/utility.hh | 27 +++++++++
diffs (truncated from 451 to 300 lines):
diff -r 29c1cc8075e4 -r 1cee707c1228 src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Sun Jun 21 09:16:55 2009 -0700
+++ b/src/arch/arm/isa/decoder.isa Sun Jun 21 09:21:07 2009 -0700
@@ -830,7 +830,7 @@
}
format PredOp {
// ARM System Call (SoftWare Interrupt)
- 1: swi({{ if (arm_predicate(xc->readMiscReg(ArmISA::CPSR),
+ 1: swi({{ if
(testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR),
condCode))
{
//xc->syscall(R7);
diff -r 29c1cc8075e4 -r 1cee707c1228 src/arch/arm/isa/formats/branch.isa
--- a/src/arch/arm/isa/formats/branch.isa Sun Jun 21 09:16:55 2009 -0700
+++ b/src/arch/arm/isa/formats/branch.isa Sun Jun 21 09:21:07 2009 -0700
@@ -234,7 +234,7 @@
else:
inst_flags += ('IsCondControl', )
- icode = 'if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode)) {\n'
+ icode = 'if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR),
condCode)) {\n'
icode += code
icode += ' NPC = NPC + 4 + disp;\n'
icode += '} else {\n'
@@ -268,7 +268,7 @@
#Condition code
- icode = 'if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode)) {\n'
+ icode = 'if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR),
condCode)) {\n'
icode += code
icode += ' NPC = Rm & 0xfffffffe; // Masks off bottom bit\n'
icode += '} else {\n'
diff -r 29c1cc8075e4 -r 1cee707c1228 src/arch/arm/isa/formats/fp.isa
--- a/src/arch/arm/isa/formats/fp.isa Sun Jun 21 09:16:55 2009 -0700
+++ b/src/arch/arm/isa/formats/fp.isa Sun Jun 21 09:21:07 2009 -0700
@@ -67,7 +67,7 @@
%(code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode) &&
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR),
condCode) &&
fault == NoFault)
{
%(op_wb)s;
diff -r 29c1cc8075e4 -r 1cee707c1228 src/arch/arm/isa/formats/mem.isa
--- a/src/arch/arm/isa/formats/mem.isa Sun Jun 21 09:16:55 2009 -0700
+++ b/src/arch/arm/isa/formats/mem.isa Sun Jun 21 09:21:07 2009 -0700
@@ -216,7 +216,7 @@
%(op_rd)s;
%(ea_code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
%(op_wb)s;
@@ -241,7 +241,7 @@
%(op_rd)s;
EA = xc->getEA();
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem,
memAccessFlags);
@@ -270,7 +270,7 @@
%(op_rd)s;
%(ea_code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem,
memAccessFlags);
@@ -299,7 +299,7 @@
%(op_rd)s;
%(ea_code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem,
memAccessFlags);
@@ -322,7 +322,7 @@
%(op_decl)s;
%(op_rd)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
// ARM instructions will not have a pkt if the predicate is false
Mem = pkt->get<typeof(Mem)>();
@@ -353,7 +353,7 @@
%(op_decl)s;
%(op_rd)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
EA = xc->getEA();
@@ -385,7 +385,7 @@
%(op_rd)s;
%(ea_code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
%(memacc_code)s;
@@ -418,7 +418,7 @@
%(op_rd)s;
%(ea_code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
%(memacc_code)s;
@@ -451,7 +451,7 @@
%(fp_enable_check)s;
%(op_dest_decl)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
%(op_wb)s;
@@ -472,7 +472,7 @@
%(fp_enable_check)s;
%(op_dest_decl)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
%(op_wb)s;
@@ -495,7 +495,7 @@
%(op_decl)s;
%(op_rd)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
EA = xc->getEA();
@@ -520,7 +520,7 @@
%(op_rd)s;
%(ea_code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault) {
%(memacc_code)s;
diff -r 29c1cc8075e4 -r 1cee707c1228 src/arch/arm/isa/formats/pred.isa
--- a/src/arch/arm/isa/formats/pred.isa Sun Jun 21 09:16:55 2009 -0700
+++ b/src/arch/arm/isa/formats/pred.isa Sun Jun 21 09:21:07 2009 -0700
@@ -36,25 +36,6 @@
output header {{
#include <iostream>
- enum ArmPredicateBits {
- COND_EQ = 0,
- COND_NE, // 1
- COND_CS, // 2
- COND_CC, // 3
- COND_MI, // 4
- COND_PL, // 5
- COND_VS, // 6
- COND_VC, // 7
- COND_HI, // 8
- COND_LS, // 9
- COND_GE, // 10
- COND_LT, // 11
- COND_GT, // 12
- COND_LE, // 13
- COND_AL, // 14
- COND_NV // 15
- };
-
inline uint32_t
rotate_imm(uint32_t immValue, uint32_t rotateValue)
{
@@ -62,76 +43,23 @@
(immValue << (32 - (int)(rotateValue & 31))));
}
- inline uint32_t nSet(uint32_t cpsr) { return cpsr & (1<<31); }
- inline uint32_t zSet(uint32_t cpsr) { return cpsr & (1<<30); }
- inline uint32_t cSet(uint32_t cpsr) { return cpsr & (1<<29); }
- inline uint32_t vSet(uint32_t cpsr) { return cpsr & (1<<28); }
-
- inline bool arm_predicate(uint32_t cpsr, uint32_t predBits)
- {
-
- enum ArmPredicateBits armPredBits = (enum ArmPredicateBits) predBits;
- uint32_t result = 0;
- switch (armPredBits)
- {
- case COND_EQ:
- result = zSet(cpsr); break;
- case COND_NE:
- result = !zSet(cpsr); break;
- case COND_CS:
- result = cSet(cpsr); break;
- case COND_CC:
- result = !cSet(cpsr); break;
- case COND_MI:
- result = nSet(cpsr); break;
- case COND_PL:
- result = !nSet(cpsr); break;
- case COND_VS:
- result = vSet(cpsr); break;
- case COND_VC:
- result = !vSet(cpsr); break;
- case COND_HI:
- result = cSet(cpsr) && !zSet(cpsr); break;
- case COND_LS:
- result = !cSet(cpsr) || zSet(cpsr); break;
- case COND_GE:
- result = (!nSet(cpsr) && !vSet(cpsr)) || (nSet(cpsr) &&
vSet(cpsr)); break;
- case COND_LT:
- result = (nSet(cpsr) && !vSet(cpsr)) || (!nSet(cpsr) &&
vSet(cpsr)); break;
- case COND_GT:
- result = (!nSet(cpsr) && !vSet(cpsr) && !zSet(cpsr)) ||
(nSet(cpsr) && vSet(cpsr) && !zSet(cpsr)); break;
- case COND_LE:
- result = (nSet(cpsr) && !vSet(cpsr)) || (!nSet(cpsr) &&
vSet(cpsr)) || zSet(cpsr); break;
- case COND_AL: result = 1; break;
- case COND_NV: result = 0; break;
- default:
- fprintf(stderr, "Unhandled predicate condition: %d\n",
armPredBits);
- exit(1);
- }
- if (result)
- return true;
- else
- return false;
- }
-
-
/**
* Base class for predicated integer operations.
*/
class PredOp : public ArmStaticInst
{
- protected:
+ protected:
- uint32_t condCode;
+ ArmISA::ConditionCode condCode;
- /// Constructor
- PredOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
- ArmStaticInst(mnem, _machInst, __opClass),
- condCode(COND_CODE)
- {
- }
+ /// Constructor
+ PredOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ ArmStaticInst(mnem, _machInst, __opClass),
+ condCode((ArmISA::ConditionCode)COND_CODE)
+ {
+ }
- std::string generateDisassembly(Addr pc, const SymbolTable
*symtab) const;
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
const;
};
/**
@@ -243,7 +171,7 @@
%(op_rd)s;
%(code)s;
- if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
+ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode))
{
if (fault == NoFault)
{
diff -r 29c1cc8075e4 -r 1cee707c1228 src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa Sun Jun 21 09:16:55 2009 -0700
+++ b/src/arch/arm/isa/operands.isa Sun Jun 21 09:21:07 2009 -0700
@@ -64,8 +64,8 @@
#Memory Operand
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
- 'Cpsr': ('ControlReg', 'uw', 'CPSR', 'IsInteger', 7),
- 'Fpsr': ('ControlReg', 'uw', 'FPSR', 'IsInteger', 7),
+ 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 7),
+ 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 7),
'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9),
'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 9),
diff -r 29c1cc8075e4 -r 1cee707c1228 src/arch/arm/miscregs.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/arm/miscregs.hh Sun Jun 21 09:21:07 2009 -0700
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
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