changeset 094b7ea0b180 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=094b7ea0b180
description:
ARM: Get rid of unnecessary Re operand.
diffstat:
2 files changed, 3 deletions(-)
src/arch/arm/isa/bitfields.isa | 2 --
src/arch/arm/isa/operands.isa | 1 -
diffs (23 lines):
diff -r 5744fafb5072 -r 094b7ea0b180 src/arch/arm/isa/bitfields.isa
--- a/src/arch/arm/isa/bitfields.isa Sun Jun 21 09:43:55 2009 -0700
+++ b/src/arch/arm/isa/bitfields.isa Sun Jun 21 09:48:44 2009 -0700
@@ -70,8 +70,6 @@
def bitfield SHIFT < 6: 5>;
def bitfield RM < 3: 0>;
-def bitfield RE <20:16>;
-
def bitfield RS <11: 8>;
def bitfield RDUP <19:16>;
diff -r 5744fafb5072 -r 094b7ea0b180 src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa Sun Jun 21 09:43:55 2009 -0700
+++ b/src/arch/arm/isa/operands.isa Sun Jun 21 09:48:44 2009 -0700
@@ -46,7 +46,6 @@
'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2),
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
- 'Re': ('IntReg', 'uw', 'RE', 'IsInteger', 5),
'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5),
'R0': ('IntReg', 'uw', '0', 'IsInteger', 5),
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