changeset 75adb07279b4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=75adb07279b4
description:
ARM: Get rid of a few more unused operands.
diffstat:
2 files changed, 4 deletions(-)
src/arch/arm/isa/decoder.isa | 1 -
src/arch/arm/isa/operands.isa | 3 ---
diffs (27 lines):
diff -r 094b7ea0b180 -r 75adb07279b4 src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Sun Jun 21 09:48:44 2009 -0700
+++ b/src/arch/arm/isa/decoder.isa Sun Jun 21 09:48:51 2009 -0700
@@ -832,7 +832,6 @@
// ARM System Call (SoftWare Interrupt)
1: swi({{ if (testPredicate(Cpsr, condCode))
{
- //xc->syscall(R7);
xc->syscall(IMMED_23_0);
}
}});
diff -r 094b7ea0b180 -r 75adb07279b4 src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa Sun Jun 21 09:48:44 2009 -0700
+++ b/src/arch/arm/isa/operands.isa Sun Jun 21 09:48:51 2009 -0700
@@ -48,12 +48,9 @@
'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5),
- 'R0': ('IntReg', 'uw', '0', 'IsInteger', 5),
- 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 5),
'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 6),
'LR': ('IntReg', 'uw', '14', 'IsInteger', 6),
- 'Ignore': ('IntReg', 'uw', '16', 'IsInteger', 99),
#General Purpose Floating Point Reg Operands
'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
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