changeset dadfc8d8b6dd in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=dadfc8d8b6dd
description:
ARM: Added unimplemented load/store multiple instructions.
diffstat:
1 file changed, 9 insertions(+), 16 deletions(-)
src/arch/arm/isa/formats/macromem.isa | 25 +++++++++----------------
diffs (57 lines):
diff -r 1ab29409ee29 -r dadfc8d8b6dd src/arch/arm/isa/formats/macromem.isa
--- a/src/arch/arm/isa/formats/macromem.isa Tue Jun 23 00:14:24 2009 -0700
+++ b/src/arch/arm/isa/formats/macromem.isa Tue Jun 23 23:23:25 2009 -0700
@@ -58,44 +58,37 @@
switch (puswl)
{
+ case 0x00: // stmda
case 0x01: // L ldmda_l
- start_addr = (ones << 2) - 4;
- end_addr = 0;
- break;
+ case 0x02: // W stmda_w
case 0x03: // WL ldmda_wl
start_addr = (ones << 2) - 4;
end_addr = 0;
break;
case 0x08: // U stmia_u
- start_addr = 0;
- end_addr = (ones << 2) - 4;
- break;
case 0x09: // U L ldmia_ul
- start_addr = 0;
- end_addr = (ones << 2) - 4;
- break;
+ case 0x0a: // U W stmia
case 0x0b: // U WL ldmia
start_addr = 0;
end_addr = (ones << 2) - 4;
break;
+ case 0x10: // P stmdb
case 0x11: // P L ldmdb
- start_addr = (ones << 2); // U-bit is already 0 for subtract
- end_addr = 4; // negative 4
- break;
case 0x12: // P W stmdb
+ case 0x13: // P WL ldmdb
start_addr = (ones << 2); // U-bit is already 0 for subtract
end_addr = 4; // negative 4
break;
case 0x18: // PU stmib
- start_addr = 4;
- end_addr = (ones << 2) + 4;
- break;
case 0x19: // PU L ldmib
+ case 0x1a: // PU W stmib
+ case 0x1b: // PU WL ldmib
start_addr = 4;
end_addr = (ones << 2) + 4;
break;
default:
- panic("Unhandled Load/Store Multiple Instruction");
+ panic("Unhandled Load/Store Multiple Instruction, "
+ "puswl = 0x%x", (unsigned) puswl);
break;
}
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