changeset 5fdf0fc147bd in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5fdf0fc147bd
description:
ARM: Fill out the printReg function.
diffstat:
2 files changed, 31 insertions(+), 4 deletions(-)
src/arch/arm/insts/static_inst.cc | 25 ++++++++++++++++++++++---
src/arch/arm/miscregs.hh | 10 +++++++++-
diffs (61 lines):
diff -r 953e39da7b53 -r 5fdf0fc147bd src/arch/arm/insts/static_inst.cc
--- a/src/arch/arm/insts/static_inst.cc Wed Jun 24 21:22:52 2009 -0700
+++ b/src/arch/arm/insts/static_inst.cc Fri Jun 26 22:01:34 2009 -0700
@@ -219,10 +219,29 @@
ArmStaticInst::printReg(std::ostream &os, int reg) const
{
if (reg < FP_Base_DepTag) {
- ccprintf(os, "r%d", reg);
- }
- else {
+ switch (reg) {
+ case PCReg:
+ ccprintf(os, "pc");
+ break;
+ case StackPointerReg:
+ ccprintf(os, "sp");
+ break;
+ case FramePointerReg:
+ ccprintf(os, "fp");
+ break;
+ case ReturnAddressReg:
+ ccprintf(os, "lr");
+ break;
+ default:
+ ccprintf(os, "r%d", reg);
+ break;
+ }
+ } else if (reg < Ctrl_Base_DepTag) {
ccprintf(os, "f%d", reg - FP_Base_DepTag);
+ } else {
+ reg -= Ctrl_Base_DepTag;
+ assert(reg < NUM_MISCREGS);
+ ccprintf(os, "%s", ArmISA::miscRegName[reg]);
}
}
diff -r 953e39da7b53 -r 5fdf0fc147bd src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh Wed Jun 24 21:22:52 2009 -0700
+++ b/src/arch/arm/miscregs.hh Fri Jun 26 22:01:34 2009 -0700
@@ -55,12 +55,20 @@
enum MiscRegIndex {
MISCREG_CPSR = 0,
+ MISCREG_SPSR,
MISCREG_SPSR_FIQ,
MISCREG_SPSR_IRQ,
MISCREG_SPSR_SVC,
MISCREG_SPSR_UND,
MISCREG_SPSR_ABT,
- MISCREG_FPSR
+ MISCREG_FPSR,
+ NUM_MISCREGS
+ };
+
+ const char * const miscRegName[NUM_MISCREGS] = {
+ "cpsr",
+ "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und", "spsr_abt",
+ "fpsr"
};
BitUnion32(CPSR)
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