changeset 8be7583b271c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8be7583b271c
description:
ARM: Decode some media instructions. These are untested.
diffstat:
3 files changed, 57 insertions(+)
src/arch/arm/isa/bitfields.isa | 2 +
src/arch/arm/isa/decoder.isa | 54 ++++++++++++++++++++++++++++++++++++++++
src/arch/arm/types.hh | 1
diffs (87 lines):
diff -r 0f869e59c079 -r 8be7583b271c src/arch/arm/isa/bitfields.isa
--- a/src/arch/arm/isa/bitfields.isa Wed Jul 01 22:11:39 2009 -0700
+++ b/src/arch/arm/isa/bitfields.isa Wed Jul 01 22:11:54 2009 -0700
@@ -37,6 +37,8 @@
def bitfield ENCODING encoding;
def bitfield OPCODE opcode;
def bitfield OPCODE_24_23 opcode24_23;
+def bitfield MEDIA_OPCODE mediaOpcode;
+def bitfield MEDIA_OPCODE2 mediaOpcode2;
def bitfield OPCODE_24 opcode24;
def bitfield OPCODE_23_20 opcode23_20;
def bitfield OPCODE_23_21 opcode23_21;
diff -r 0f869e59c079 -r 8be7583b271c src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Wed Jul 01 22:11:39 2009 -0700
+++ b/src/arch/arm/isa/decoder.isa Wed Jul 01 22:11:54 2009 -0700
@@ -566,6 +566,60 @@
Rn = Rn + Rm_Imm; }},
{{ EA = Rn + Rm_Imm; }});
}
+ 1: decode MEDIA_OPCODE {
+ 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7:
WarnUnimpl::parallel_add_subtract_instructions();
+ 0x8: decode MISC_OPCODE {
+ 0x1, 0x9: WarnUnimpl::pkhbt();
+ 0x7: WarnUnimpl::sxtab16();
+ 0xb: WarnUnimpl::sel();
+ 0x5, 0xd: WarnUnimpl::pkhtb();
+ 0x3: WarnUnimpl::sign_zero_extend_add();
+ }
+ 0xa, 0xb: decode SHIFT {
+ 0x0, 0x2: WarnUnimpl::ssat();
+ 0x1: WarnUnimpl::ssat16();
+ }
+ 0xe, 0xf: decode SHIFT {
+ 0x0, 0x2: WarnUnimpl::usat();
+ 0x1: WarnUnimpl::usat16();
+ }
+ 0x10: decode RN {
+ 0xf: decode MISC_OPCODE {
+ 0x1: WarnUnimpl::smuad();
+ 0x3: WarnUnimpl::smuadx();
+ 0x5: WarnUnimpl::smusd();
+ 0x7: WarnUnimpl::smusdx();
+ }
+ default: decode MISC_OPCODE {
+ 0x1: WarnUnimpl::smlad();
+ 0x3: WarnUnimpl::smladx();
+ 0x5: WarnUnimpl::smlsd();
+ 0x7: WarnUnimpl::smlsdx();
+ }
+ }
+ 0x14: decode MISC_OPCODE {
+ 0x1: WarnUnimpl::smlald();
+ 0x3: WarnUnimpl::smlaldx();
+ 0x5: WarnUnimpl::smlsld();
+ 0x7: WarnUnimpl::smlsldx();
+ }
+ 0x15: decode RN {
+ 0xf: decode MISC_OPCODE {
+ 0x1: WarnUnimpl::smmul();
+ 0x3: WarnUnimpl::smmulr();
+ }
+ default: decode MISC_OPCODE {
+ 0x1: WarnUnimpl::smmla();
+ 0x3: WarnUnimpl::smmlar();
+ 0xd: WarnUnimpl::smmls();
+ 0xf: WarnUnimpl::smmlsr();
+ }
+ }
+ 0x18: decode RN {
+ 0xf: WarnUnimpl::usada8();
+ default: WarnUnimpl::usad8();
+ }
+ }
}
0x4: decode PUSWL {
// Right now we only handle cases when S (PSRUSER) is not set
diff -r 0f869e59c079 -r 8be7583b271c src/arch/arm/types.hh
--- a/src/arch/arm/types.hh Wed Jul 01 22:11:39 2009 -0700
+++ b/src/arch/arm/types.hh Wed Jul 01 22:11:54 2009 -0700
@@ -46,6 +46,7 @@
// All the different types of opcode fields.
Bitfield<27, 25> encoding;
Bitfield<24, 21> opcode;
+ Bitfield<24, 20> mediaOpcode;
Bitfield<24, 23> opcode24_23;
Bitfield<24> opcode24;
Bitfield<23, 20> opcode23_20;
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