changeset 0f869e59c079 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0f869e59c079
description:
ARM: Use the new DataOp format to simplify the decoder.
diffstat:
4 files changed, 543 insertions(+), 641 deletions(-)
src/arch/arm/insts/static_inst.cc | 2
src/arch/arm/isa/bitfields.isa | 5
src/arch/arm/isa/decoder.isa | 1170 ++++++++++++++++---------------------
src/arch/arm/types.hh | 7
diffs (truncated from 1287 to 300 lines):
diff -r f5edd0f709e4 -r 0f869e59c079 src/arch/arm/insts/static_inst.cc
--- a/src/arch/arm/insts/static_inst.cc Wed Jul 01 22:11:27 2009 -0700
+++ b/src/arch/arm/insts/static_inst.cc Wed Jul 01 22:11:39 2009 -0700
@@ -388,7 +388,7 @@
{
printMnemonic(os, machInst.sField ? "s" : "");
//XXX It would be nice if the decoder figured this all out for us.
- unsigned opcode = machInst.opcode24_21;
+ unsigned opcode = machInst.opcode;
bool firstOp = true;
// Destination
diff -r f5edd0f709e4 -r 0f869e59c079 src/arch/arm/isa/bitfields.isa
--- a/src/arch/arm/isa/bitfields.isa Wed Jul 01 22:11:27 2009 -0700
+++ b/src/arch/arm/isa/bitfields.isa Wed Jul 01 22:11:39 2009 -0700
@@ -34,9 +34,8 @@
//
// Opcode fields
+def bitfield ENCODING encoding;
def bitfield OPCODE opcode;
-def bitfield OPCODE_27_25 opcode27_25;
-def bitfield OPCODE_24_21 opcode24_21;
def bitfield OPCODE_24_23 opcode24_23;
def bitfield OPCODE_24 opcode24;
def bitfield OPCODE_23_20 opcode23_20;
@@ -52,7 +51,7 @@
def bitfield OPCODE_15_12 opcode15_12;
def bitfield OPCODE_15 opcode15;
def bitfield OPCODE_9 opcode9;
-def bitfield OPCODE_7_4 opcode7_4;
+def bitfield MISC_OPCODE miscOpcode;
def bitfield OPCODE_7_5 opcode7_5;
def bitfield OPCODE_7_6 opcode7_6;
def bitfield OPCODE_7 opcode7;
diff -r f5edd0f709e4 -r 0f869e59c079 src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Wed Jul 01 22:11:27 2009 -0700
+++ b/src/arch/arm/isa/decoder.isa Wed Jul 01 22:11:39 2009 -0700
@@ -39,7 +39,7 @@
//
decode COND_CODE default Unknown::unknown() {
0xf: decode COND_CODE {
- 0x0: decode OPCODE_27_25 {
+ 0x0: decode OPCODE {
// Just a simple trick to allow us to specify our new uops here
0x0: PredImmOp::addi_uop({{ Raddr = Rn + rotated_imm; }},
'IsMicroop');
@@ -56,7 +56,7 @@
0x5: PredImmOp::subi_rd_uop({{ Rd = Rn - rotated_imm; }},
'IsMicroop');
}
- 0x1: decode OPCODE_27_25 {
+ 0x1: decode OPCODE {
0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi << 32)|Rlo; }},
'IsMicroop');
0x1: PredIntOp::mvfd_uop({{ Rhi = (Fd.ud >> 32) & 0xffffffff;
@@ -77,394 +77,289 @@
}
default: Unknown::unknown(); // TODO: Ignore other NV space for now
}
- format BasicOp{
- default: decode OPCODE_27_25 {
- 0x0: decode OPCODE_4 {
- 0: decode S_FIELD {
- 0: decode OPCODE_24_21 {
- format PredIntOp {
- 0x0: and({{ Rd = Rn & Rm_Imm; }});
- 0x1: eor({{ Rd = Rn ^ Rm_Imm; }});
- 0x2: sub({{ Rd = Rn - Rm_Imm; }});
- 0x3: rsb({{ Rd = Rm_Imm - Rn; }});
- 0x4: add({{ Rd = Rn + Rm_Imm; }});
- 0x5: adc({{ Rd = Rn + Rm_Imm + Cpsr<29:>; }});
- 0x6: sbc({{ Rd = Rn - Rm_Imm + Cpsr<29:> - 1; }});
- 0x7: rsc({{ Rd = Rm_Imm - Rn + Cpsr<29:> - 1; }});
- //0x8:mrs_cpsr -- TODO
- //0x9:msr_cpsr -- TODO
- //0xa:mrs_spsr -- TODO
- //0xb:msr_spsr -- TODO
- 0xc: orr({{ Rd = Rn | Rm_Imm; }});
- 0xd: mov({{ Rd = Rm_Imm; }});
- 0xe: bic({{ Rd = Rn & ~Rm_Imm; }});
- 0xf: mvn({{ Rd = ~Rm_Imm; }});
- }
+default: decode ENCODING {
+format DataOp {
+ 0x0: decode SEVEN_AND_FOUR {
+ 1: decode MISC_OPCODE {
+ 0x9: decode PREPOST {
+ 0: decode OPCODE {
+ 0x0: mul({{ uint32_t resTemp;
+ Rn = resTemp = Rm * Rs; }},
+ {{ Cpsr<29:> }},
+ {{ Cpsr<28:> }});
+ 0x1: mla({{ uint32_t resTemp;
+ Rn = resTemp = Rm * Rs; }},
+ {{ Cpsr<29:> }},
+ {{ Cpsr<28:> }});
+ 0x2: WarnUnimpl::umall();
+ 0x4: umull({{
+ uint64_t resTemp;
+ resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
+ Rd = (uint32_t)(resTemp & 0xffffffff);
+ Rn = (uint32_t)(resTemp >> 32);
+ }}, {{ 1 }}, {{ 1 }});
+ 0x5: WarnUnimpl::smlal();
+ 0x6: smull({{
+ int64_t resTemp;
+ resTemp = ((int64_t)Rm.sw)*((int64_t)Rs.sw);
+ Rd = (int32_t)(resTemp & 0xffffffff);
+ Rn = (int32_t)(resTemp >> 32);
+ }}, {{ 1 }}, {{ 1 }});
+ 0x7: umlal({{
+ uint64_t resTemp;
+ resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
+ resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
+ Rd = (uint32_t)(resTemp & 0xffffffff);
+ Rn = (uint32_t)(resTemp >> 32);
+ }}, {{ 1 }}, {{ 1 }});
}
- 1: decode OPCODE_24_21 {
- format PredIntOpCc {
- 0x0: ands({{
- uint32_t resTemp;
- Rd = resTemp = Rn & Rm_Imm;
- }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
- 0x1: eors({{
- uint32_t resTemp;
- Rd = resTemp = Rn ^ Rm_Imm;
- }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
- 0x2: subs({{
- uint32_t resTemp,
- val2 = Rm_Imm;
- Rd = resTemp = Rn - val2;
- }},
- {{ arm_sub_carry(resTemp, Rn, val2) }},
- {{ arm_sub_overflow(resTemp, Rn, val2) }});
- 0x3: rsbs({{
- uint32_t resTemp,
- val2 = Rm_Imm;
- Rd = resTemp = val2 - Rn;
- }},
- {{ arm_sub_carry(resTemp, val2, Rn) }},
- {{ arm_sub_overflow(resTemp, val2, Rn) }});
- 0x4: adds({{
- uint32_t resTemp,
- val2 = Rm_Imm;
- Rd = resTemp = Rn + val2;
- }},
- {{ arm_add_carry(resTemp, Rn, val2) }},
- {{ arm_add_overflow(resTemp, Rn, val2) }});
- 0x5: adcs({{
- uint32_t resTemp,
- val2 = Rm_Imm;
- Rd = resTemp = Rn + val2 + Cpsr<29:>;
- }},
- {{ arm_add_carry(resTemp, Rn, val2) }},
- {{ arm_add_overflow(resTemp, Rn, val2) }});
- 0x6: sbcs({{
- uint32_t resTemp,
- val2 = Rm_Imm;
- Rd = resTemp = Rn - val2 + Cpsr<29:> - 1;
- }},
- {{ arm_sub_carry(resTemp, Rn, val2) }},
- {{ arm_sub_overflow(resTemp, Rn, val2) }});
- 0x7: rscs({{
- uint32_t resTemp,
- val2 = Rm_Imm;
- Rd = resTemp = val2 - Rn + Cpsr<29:> - 1;
- }},
- {{ arm_sub_carry(resTemp, val2, Rn) }},
- {{ arm_sub_overflow(resTemp, val2, Rn) }});
- 0x8: tst({{
- uint32_t resTemp;
- resTemp = Rn & Rm_Imm;
- }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
- 0x9: teq({{
- uint32_t resTemp;
- resTemp = Rn ^ Rm_Imm;
- }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
- 0xa: cmp({{
- uint32_t resTemp,
- val2 = Rm_Imm;
- resTemp = Rn - val2;
- }},
- {{ arm_sub_carry(resTemp, Rn, val2) }},
- {{ arm_sub_overflow(resTemp, Rn, val2) }});
- 0xb: cmn({{
- uint32_t resTemp,
- val2 = Rm_Imm;
- resTemp = Rn + val2;
- }},
- {{ arm_add_carry(resTemp, Rn, val2) }},
- {{ arm_add_overflow(resTemp, Rn, val2) }});
- 0xc: orrs({{
- uint32_t resTemp,
- val2 = Rm_Imm;
- Rd = resTemp = Rn | val2;
- }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
- 0xd: movs({{
- uint32_t resTemp;
- Rd = resTemp = Rm_Imm;
- }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
- 0xe: bics({{
- uint32_t resTemp;
- Rd = resTemp = Rn & ~Rm_Imm;
- }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
- 0xf: mvns({{
- uint32_t resTemp;
- Rd = resTemp = ~Rm_Imm;
- }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
- }
+ 1: decode PUBWL {
+ 0x10: WarnUnimpl::swp();
+ 0x14: WarnUnimpl::swpb();
+ 0x18: WarnUnimpl::strex();
+ 0x19: WarnUnimpl::ldrex();
}
}
- 1: decode OPCODE_7 {
- 0: decode S_FIELD {
- 0: decode OPCODE_24_21 {
- format PredIntOp {
- 0x0: and_rs({{ Rd = Rn & Rm_Rs; }});
- 0x1: eor_rs({{ Rd = Rn ^ Rm_Rs; }});
- 0x2: sub_rs({{ Rd = Rn - Rm_Rs; }});
- 0x3: rsb_rs({{ Rd = Rm_Rs - Rn; }});
- 0x4: add_rs({{ Rd = Rn + Rm_Rs; }});
- 0x5: adc_rs({{ Rd = Rn + Rm_Rs + Cpsr<29:>; }});
- 0x6: sbc_rs({{ Rd = Rn - Rm_Rs + Cpsr<29:> - 1; }});
- 0x7: rsc_rs({{ Rd = Rm_Rs - Rn + Cpsr<29:> - 1; }});
- 0xc: orr_rs({{ Rd = Rn | Rm_Rs; }});
- 0xd: mov_rs({{ Rd = Rm_Rs; }});
- 0xe: bic_rs({{ Rd = Rn & ~Rm_Rs; }});
- 0xf: mvn_rs({{ Rd = ~Rm_Rs; }});
- default: decode OPCODE_7_4 {
- 0x1: decode OPCODE_24_21 {
- 0x9: BranchExchange::bx({{ }});
- 0xb: PredOp::clz({{
- if (Rm == 0)
- Rd = 32;
- else
- {
- int i;
- for (i = 0; i < 32; i++)
- {
- if (Rm & (1<<(31-i)))
- break;
- }
- Rd = i;
- }
- }});
- }
- 0x3: decode OPCODE_24_21 {
- 0x9: BranchExchange::blx({{ }}, Link);
- }
- }
- }
- }
- 1: decode OPCODE_24_21 {
- format PredIntOpCc {
- 0x0: ands_rs({{
- uint32_t resTemp;
- Rd = resTemp = Rn & Rm_Rs;
- }},
- {{ shift_carry_rs(Rm, Rs, shift, Cpsr<29:>) }},
- {{ Cpsr<28:> }});
- 0x1: eors_rs({{
- uint32_t resTemp;
- Rd = resTemp = Rn ^ Rm_Rs;
- }},
- {{ shift_carry_rs(Rm, Rs, shift, Cpsr<29:>) }},
- {{ Cpsr<28:> }});
- 0x2: subs_rs({{
- uint32_t resTemp,
- val2 = Rm_Rs;
- Rd = resTemp = Rn - val2;
- }},
- {{ arm_sub_carry(resTemp, Rn, val2) }},
- {{ arm_sub_overflow(resTemp, Rn, val2) }});
- 0x3: rsbs_rs({{
- uint32_t resTemp,
- val2 = Rm_Rs;
- Rd = resTemp = val2 - Rn;
- }},
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