changeset fa79e8f9ab41 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=fa79e8f9ab41
description:
ARM: Get rid of the val2 variable.
diffstat:
2 files changed, 33 insertions(+), 39 deletions(-)
src/arch/arm/isa/decoder.isa | 62 ++++++++++++++++---------------------
src/arch/arm/isa/formats/pred.isa | 10 +++--
diffs (105 lines):
diff -r d0fb87f3318e -r fa79e8f9ab41 src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Wed Jul 01 22:15:39 2009 -0700
+++ b/src/arch/arm/isa/decoder.isa Wed Jul 01 22:16:05 2009 -0700
@@ -97,7 +97,8 @@
}}, {{ 1 }}, {{ 1 }});
0x5: WarnUnimpl::smlal();
0x6: smull({{
- resTemp = ((int64_t)Rm.sw)*((int64_t)Rs.sw);
+ resTemp = ((int64_t)(int32_t)Rm)*
+ ((int64_t)(int32_t)Rs);
Rd = (int32_t)(resTemp & 0xffffffff);
Rn = (int32_t)(resTemp >> 32);
}}, {{ 1 }}, {{ 1 }});
@@ -232,46 +233,37 @@
0x1: eor({{ Rd = resTemp = Rn ^ op2; }},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
{{ Cpsr<28:> }});
- 0x2: sub({{ uint32_t val2 = op2;
- Rd = resTemp = Rn - val2; }},
- {{ arm_sub_carry(resTemp, Rn, val2) }},
- {{ arm_sub_overflow(resTemp, Rn, val2) }});
- 0x3: rsb({{ uint32_t val2 = op2;
- Rd = resTemp = val2 - Rn; }},
- {{ arm_sub_carry(resTemp, val2, Rn) }},
- {{ arm_sub_overflow(resTemp, val2, Rn) }});
- 0x4: add({{ uint32_t val2 = op2;
- Rd = resTemp = Rn + val2; }},
- {{ arm_add_carry(resTemp, Rn, val2) }},
- {{ arm_add_overflow(resTemp, Rn, val2) }});
- 0x5: adc({{ uint32_t val2 = op2;
- Rd = resTemp = Rn + val2 + Cpsr<29:>; }},
- {{ arm_add_carry(resTemp, Rn, val2) }},
- {{ arm_add_overflow(resTemp, Rn, val2) }});
- 0x6: sbc({{ uint32_t val2 = op2;
- Rd = resTemp = Rn - val2 - !Cpsr<29:>; }},
- {{ arm_sub_carry(resTemp, Rn, val2) }},
- {{ arm_sub_overflow(resTemp, Rn, val2) }});
- 0x7: rsc({{ uint32_t val2 = op2;
- Rd = resTemp = val2 - Rn - !Cpsr<29:>; }},
- {{ arm_sub_carry(resTemp, val2, Rn) }},
- {{ arm_sub_overflow(resTemp, val2, Rn) }});
+ 0x2: sub({{ Rd = resTemp = Rn - op2; }},
+ {{ arm_sub_carry(resTemp, Rn, op2) }},
+ {{ arm_sub_overflow(resTemp, Rn, op2) }});
+ 0x3: rsb({{ Rd = resTemp = op2 - Rn; }},
+ {{ arm_sub_carry(resTemp, op2, Rn) }},
+ {{ arm_sub_overflow(resTemp, op2, Rn) }});
+ 0x4: add({{ Rd = resTemp = Rn + op2; }},
+ {{ arm_add_carry(resTemp, Rn, op2) }},
+ {{ arm_add_overflow(resTemp, Rn, op2) }});
+ 0x5: adc({{ Rd = resTemp = Rn + op2 + Cpsr<29:>; }},
+ {{ arm_add_carry(resTemp, Rn, op2) }},
+ {{ arm_add_overflow(resTemp, Rn, op2) }});
+ 0x6: sbc({{ Rd = resTemp = Rn - op2 - !Cpsr<29:>; }},
+ {{ arm_sub_carry(resTemp, Rn, op2) }},
+ {{ arm_sub_overflow(resTemp, Rn, op2) }});
+ 0x7: rsc({{ Rd = resTemp = op2 - Rn - !Cpsr<29:>; }},
+ {{ arm_sub_carry(resTemp, op2, Rn) }},
+ {{ arm_sub_overflow(resTemp, op2, Rn) }});
0x8: tst({{ resTemp = Rn & op2; }},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
{{ Cpsr<28:> }});
0x9: teq({{ resTemp = Rn ^ op2; }},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
{{ Cpsr<28:> }});
- 0xa: cmp({{ uint32_t val2 = op2;
- resTemp = Rn - val2; }},
- {{ arm_sub_carry(resTemp, Rn, val2) }},
- {{ arm_sub_overflow(resTemp, Rn, val2) }});
- 0xb: cmn({{ uint32_t val2 = op2;
- resTemp = Rn + val2; }},
- {{ arm_add_carry(resTemp, Rn, val2) }},
- {{ arm_add_overflow(resTemp, Rn, val2) }});
- 0xc: orr({{ uint32_t val2 = op2;
- Rd = resTemp = Rn | val2; }},
+ 0xa: cmp({{ resTemp = Rn - op2; }},
+ {{ arm_sub_carry(resTemp, Rn, op2) }},
+ {{ arm_sub_overflow(resTemp, Rn, op2) }});
+ 0xb: cmn({{ resTemp = Rn + op2; }},
+ {{ arm_add_carry(resTemp, Rn, op2) }},
+ {{ arm_add_overflow(resTemp, Rn, op2) }});
+ 0xc: orr({{ Rd = resTemp = Rn | op2; }},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
{{ Cpsr<28:> }});
0xd: mov({{ Rd = resTemp = op2; }},
diff -r d0fb87f3318e -r fa79e8f9ab41 src/arch/arm/isa/formats/pred.isa
--- a/src/arch/arm/isa/formats/pred.isa Wed Jul 01 22:15:39 2009 -0700
+++ b/src/arch/arm/isa/formats/pred.isa Wed Jul 01 22:16:05 2009 -0700
@@ -102,10 +102,12 @@
}};
def format DataOp(code, icValue, ivValue) {{
- regCode = re.sub(r'op2', 'shift_rm_rs(Rm, Rs, \
- shift, Cpsr<29:0>)', code)
- immCode = re.sub(r'op2', 'shift_rm_imm(Rm, shift_size, \
- shift, Cpsr<29:0>)', code)
+ regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs,
+ shift, Cpsr<29:0>);
+ op2 = op2;''' + code
+ immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
+ shift, Cpsr<29:0>);
+ op2 = op2;''' + code
regIop = InstObjParams(name, Name, 'PredIntOp',
{"code": regCode,
"predicate_test": predicateTest})
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