changeset e46f6767b2c0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e46f6767b2c0
description:
ARM: Add defaults for DataOp flag code.
diffstat:
2 files changed, 33 insertions(+), 52 deletions(-)
src/arch/arm/isa/decoder.isa | 64 +++++++++----------------------------
src/arch/arm/isa/formats/pred.isa | 21 +++++++++---
diffs (160 lines):
diff -r fa79e8f9ab41 -r e46f6767b2c0 src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Wed Jul 01 22:16:05 2009 -0700
+++ b/src/arch/arm/isa/decoder.isa Wed Jul 01 22:16:19 2009 -0700
@@ -227,12 +227,8 @@
}
0: decode IS_MISC {
0: decode OPCODE {
- 0x0: and({{ Rd = resTemp = Rn & op2; }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
- 0x1: eor({{ Rd = resTemp = Rn ^ op2; }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
+ 0x0: and({{ Rd = resTemp = Rn & op2; }});
+ 0x1: eor({{ Rd = resTemp = Rn ^ op2; }});
0x2: sub({{ Rd = resTemp = Rn - op2; }},
{{ arm_sub_carry(resTemp, Rn, op2) }},
{{ arm_sub_overflow(resTemp, Rn, op2) }});
@@ -251,30 +247,18 @@
0x7: rsc({{ Rd = resTemp = op2 - Rn - !Cpsr<29:>; }},
{{ arm_sub_carry(resTemp, op2, Rn) }},
{{ arm_sub_overflow(resTemp, op2, Rn) }});
- 0x8: tst({{ resTemp = Rn & op2; }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
- 0x9: teq({{ resTemp = Rn ^ op2; }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
+ 0x8: tst({{ resTemp = Rn & op2; }});
+ 0x9: teq({{ resTemp = Rn ^ op2; }});
0xa: cmp({{ resTemp = Rn - op2; }},
{{ arm_sub_carry(resTemp, Rn, op2) }},
{{ arm_sub_overflow(resTemp, Rn, op2) }});
0xb: cmn({{ resTemp = Rn + op2; }},
{{ arm_add_carry(resTemp, Rn, op2) }},
{{ arm_add_overflow(resTemp, Rn, op2) }});
- 0xc: orr({{ Rd = resTemp = Rn | op2; }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
- 0xd: mov({{ Rd = resTemp = op2; }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
- 0xe: bic({{ Rd = resTemp = Rn & ~op2; }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
- 0xf: mvn({{ Rd = resTemp = ~op2; }},
- {{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)
}},
- {{ Cpsr<28:> }});
+ 0xc: orr({{ Rd = resTemp = Rn | op2; }});
+ 0xd: mov({{ Rd = resTemp = op2; }});
+ 0xe: bic({{ Rd = resTemp = Rn & ~op2; }});
+ 0xf: mvn({{ Rd = resTemp = ~op2; }});
}
1: decode MISC_OPCODE {
0x0: decode OPCODE {
@@ -342,12 +326,8 @@
0x1: decode IS_MISC {
0: decode OPCODE {
format DataImmOp {
- 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }},
- {{ (rotate ? rotated_carry:Cpsr<29:>) }},
- {{ Cpsr<28:> }});
- 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }},
- {{ (rotate ? rotated_carry:Cpsr<29:>) }},
- {{ Cpsr<28:> }});
+ 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }});
+ 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }});
0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }},
{{ arm_sub_carry(resTemp, Rn, rotated_imm) }},
{{ arm_sub_overflow(resTemp, Rn, rotated_imm) }});
@@ -366,30 +346,18 @@
0x7: rsci({{ Rd = resTemp = rotated_imm - Rn - !Cpsr<29:>;}},
{{ arm_sub_carry(resTemp, rotated_imm, Rn) }},
{{ arm_sub_overflow(resTemp, rotated_imm, Rn) }});
- 0x8: tsti({{ resTemp = Rn & rotated_imm; }},
- {{ (rotate ? rotated_carry:Cpsr<29:>) }},
- {{ Cpsr<28:> }});
- 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }},
- {{ (rotate ? rotated_carry:Cpsr<29:>) }},
- {{ Cpsr<28:> }});
+ 0x8: tsti({{ resTemp = Rn & rotated_imm; }});
+ 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }});
0xa: cmpi({{ resTemp = Rn - rotated_imm; }},
{{ arm_sub_carry(resTemp, Rn, rotated_imm) }},
{{ arm_sub_overflow(resTemp, Rn, rotated_imm) }});
0xb: cmni({{ resTemp = Rn + rotated_imm; }},
{{ arm_add_carry(resTemp, Rn, rotated_imm) }},
{{ arm_add_overflow(resTemp, Rn, rotated_imm) }});
- 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }},
- {{ (rotate ? rotated_carry:Cpsr<29:>) }},
- {{ Cpsr<28:> }});
- 0xd: movi({{ Rd = resTemp = rotated_imm; }},
- {{ (rotate ? rotated_carry:Cpsr<29:>) }},
- {{ Cpsr<28:> }});
- 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }},
- {{ (rotate ? rotated_carry:Cpsr<29:>) }},
- {{ Cpsr<28:> }});
- 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }},
- {{ (rotate ? rotated_carry:Cpsr<29:>) }},
- {{ Cpsr<28:> }});
+ 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }});
+ 0xd: movi({{ Rd = resTemp = rotated_imm; }});
+ 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }});
+ 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }});
}
}
1: decode OPCODE {
diff -r fa79e8f9ab41 -r e46f6767b2c0 src/arch/arm/isa/formats/pred.isa
--- a/src/arch/arm/isa/formats/pred.isa Wed Jul 01 22:16:05 2009 -0700
+++ b/src/arch/arm/isa/formats/pred.isa Wed Jul 01 22:16:19 2009 -0700
@@ -101,13 +101,24 @@
}};
-def format DataOp(code, icValue, ivValue) {{
+def format DataOp(code, icValue = {{ }},
+ ivValue = {{ Cpsr<28:> }}) {{
regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs,
shift, Cpsr<29:0>);
op2 = op2;''' + code
immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
shift, Cpsr<29:0>);
op2 = op2;''' + code
+ if icValue == " ":
+ icValueReg = 'shift_carry_rs(Rm, Rs, shift, Cpsr<29:>)'
+ icValueImm = 'shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)'
+ else:
+ icValueReg = icValue
+ icValueImm = icValue
+ regCcCode = calcCcCode % {"icValue" : icValueReg,
+ "ivValue" : ivValue}
+ immCcCode = calcCcCode % {"icValue" : icValueImm,
+ "ivValue" : ivValue}
regIop = InstObjParams(name, Name, 'PredIntOp',
{"code": regCode,
"predicate_test": predicateTest})
@@ -115,10 +126,10 @@
{"code": immCode,
"predicate_test": predicateTest})
regCcIop = InstObjParams(name, Name + "Cc", 'PredIntOp',
- {"code": regCode + calcCcCode % vars(),
+ {"code": regCode + regCcCode,
"predicate_test": predicateTest})
immCcIop = InstObjParams(name, Name + "ImmCc", 'PredIntOp',
- {"code": immCode + calcCcCode % vars(),
+ {"code": immCode + immCcCode,
"predicate_test": predicateTest})
header_output = BasicDeclare.subst(regIop) + \
BasicDeclare.subst(immIop) + \
@@ -135,7 +146,9 @@
decode_block = DataDecode.subst(regIop)
}};
-def format DataImmOp(code, icValue, ivValue) {{
+def format DataImmOp(code,
+ icValue = {{ (rotate ? rotated_carry:Cpsr<29:>) }},
+ ivValue = {{ Cpsr<28:> }}) {{
code += "resTemp = resTemp;"
iop = InstObjParams(name, Name, 'PredImmOp',
{"code": code,
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