changeset 117dbbf0e1e2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=117dbbf0e1e2
description:
ARM: Add a findLsbSet function and use it to implement clz.
diffstat:
2 files changed, 19 insertions(+), 12 deletions(-)
src/arch/arm/isa/decoder.isa | 14 ++------------
src/base/bitfield.hh | 17 +++++++++++++++++
diffs (49 lines):
diff -r e46f6767b2c0 -r 117dbbf0e1e2 src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Wed Jul 01 22:16:19 2009 -0700
+++ b/src/arch/arm/isa/decoder.isa Wed Jul 01 22:16:36 2009 -0700
@@ -270,18 +270,8 @@
0x1: decode OPCODE {
0x9: BranchExchange::bx({{ }});
0xb: PredOp::clz({{
- if (Rm == 0)
- Rd = 32;
- else
- {
- int i;
- for (i = 0; i < 32; i++)
- {
- if (Rm & (1<<(31-i)))
- break;
- }
- Rd = i;
- }
+ unsigned lsb = findLsbSet(Rm);
+ Rd = (lsb > 31) ? 32 : lsb;
}});
}
0x2: decode OPCODE {
diff -r e46f6767b2c0 -r 117dbbf0e1e2 src/base/bitfield.hh
--- a/src/base/bitfield.hh Wed Jul 01 22:16:19 2009 -0700
+++ b/src/base/bitfield.hh Wed Jul 01 22:16:36 2009 -0700
@@ -161,4 +161,21 @@
return msb;
}
+/**
+ * Returns the bit position of the LSB that is set in the input
+ */
+inline int
+findLsbSet(uint64_t val) {
+ int lsb = 0;
+ if (!val)
+ return sizeof(val) * 8;
+ if (!bits(val, 31,0)) { lsb += 32; val >>= 32; }
+ if (!bits(val, 15,0)) { lsb += 16; val >>= 16; }
+ if (!bits(val, 7,0)) { lsb += 8; val >>= 8; }
+ if (!bits(val, 3,0)) { lsb += 4; val >>= 4; }
+ if (!bits(val, 1,0)) { lsb += 2; val >>= 2; }
+ if (!bits(val, 0,0)) { lsb += 1; }
+ return lsb;
+}
+
#endif // __BASE_BITFIELD_HH__
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