changeset 31c067ae3331 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=31c067ae3331
description:
MIPS: Format the register index constants like the other ISAs.
Also a few more style fixes.
diffstat:
14 files changed, 444 insertions(+), 434 deletions(-)
src/arch/mips/faults.cc | 124 +++++++--------
src/arch/mips/interrupts.cc | 16 +-
src/arch/mips/isa.cc | 189 +++++++++++------------
src/arch/mips/isa/decoder.isa | 58 +++----
src/arch/mips/isa/formats/control.isa | 10 -
src/arch/mips/isa/formats/dsp.isa | 4
src/arch/mips/isa/formats/fp.isa | 9 -
src/arch/mips/isa/formats/mt.isa | 12 -
src/arch/mips/isa/operands.isa | 103 ++++++------
src/arch/mips/locked_mem.hh | 10 -
src/arch/mips/mt.hh | 71 ++++----
src/arch/mips/registers.hh | 262 ++++++++++++++++-----------------
src/arch/mips/tlb.cc | 6
src/arch/mips/utility.hh | 4
diffs (truncated from 1790 to 300 lines):
diff -r 9bbcb643f303 -r 31c067ae3331 src/arch/mips/faults.cc
--- a/src/arch/mips/faults.cc Tue Jul 21 21:27:54 2009 -0500
+++ b/src/arch/mips/faults.cc Tue Jul 21 23:38:26 2009 -0700
@@ -178,18 +178,18 @@
MipsFault::setExceptionState(ThreadContext *tc, uint8_t excCode)
{
// modify SRS Ctl - Save CSS, put ESS into CSS
- StatusReg status = tc->readMiscReg(Status);
+ StatusReg status = tc->readMiscReg(MISCREG_STATUS);
if (status.exl != 1 && status.bev != 1) {
// SRS Ctl is modified only if Status_EXL and Status_BEV are not set
- SRSCtlReg srsCtl = tc->readMiscReg(SRSCtl);
+ SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
srsCtl.pss = srsCtl.css;
srsCtl.css = srsCtl.ess;
- tc->setMiscRegNoEffect(SRSCtl, srsCtl);
+ tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
}
// set EXL bit (don't care if it is already set!)
status.exl = 1;
- tc->setMiscRegNoEffect(Status, status);
+ tc->setMiscRegNoEffect(MISCREG_STATUS, status);
// write EPC
// CHECK ME or FIXME or FIX ME or POSSIBLE HACK
@@ -198,21 +198,21 @@
tc->readPC(), tc->readNextPC(), tc->readNextNPC());
int bd = 0;
if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) {
- tc->setMiscRegNoEffect(EPC, tc->readPC() - sizeof(MachInst));
+ tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC() - sizeof(MachInst));
// In the branch delay slot? set CAUSE_31
bd = 1;
} else {
- tc->setMiscRegNoEffect(EPC, tc->readPC());
+ tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC());
// In the branch delay slot? reset CAUSE_31
bd = 0;
}
// Set Cause_EXCCODE field
- CauseReg cause = tc->readMiscReg(Cause);
+ CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
cause.excCode = excCode;
cause.bd = bd;
cause.ce = 0;
- tc->setMiscRegNoEffect(Cause, cause);
+ tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
}
void
@@ -223,12 +223,12 @@
// Set new PC
Addr HandlerBase;
- StatusReg status = tc->readMiscReg(Status);
+ StatusReg status = tc->readMiscReg(MISCREG_STATUS);
// Here, the handler is dependent on BEV, which is not modified by
// setExceptionState()
if (!status.bev) {
// See MIPS ARM Vol 3, Revision 2, Page 38
- HandlerBase = vect() + tc->readMiscReg(EBase);
+ HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
} else {
HandlerBase = 0xBFC00200;
}
@@ -240,12 +240,12 @@
{
DPRINTF(MipsPRA, "%s encountered.\n", name());
setExceptionState(tc, 0x5);
- tc->setMiscRegNoEffect(BadVAddr, badVAddr);
+ tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
// Set new PC
Addr HandlerBase;
// Offset 0x180 - General Exception Vector
- HandlerBase = vect() + tc->readMiscReg(EBase);
+ HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
setHandlerPC(HandlerBase, tc);
}
@@ -258,7 +258,7 @@
// Set new PC
Addr HandlerBase;
// Offset 0x180 - General Exception Vector
- HandlerBase = vect() + tc->readMiscReg(EBase);
+ HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
setHandlerPC(HandlerBase, tc);
}
@@ -270,7 +270,7 @@
// Set new PC
Addr HandlerBase;
// Offset 0x180 - General Exception Vector
- HandlerBase = vect() + tc->readMiscReg(EBase);
+ HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
setHandlerPC(HandlerBase, tc);
}
@@ -279,23 +279,23 @@
{
DPRINTF(MipsPRA, "%s encountered.\n", name());
- tc->setMiscRegNoEffect(BadVAddr, badVAddr);
- EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+ tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
+ EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
entryHi.asid = entryHiAsid;
entryHi.vpn2 = entryHiVPN2;
entryHi.vpn2x = entryHiVPN2X;
- tc->setMiscRegNoEffect(EntryHi, entryHi);
+ tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
- ContextReg context = tc->readMiscReg(Context);
+ ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
context.badVPN2 = contextBadVPN2;
- tc->setMiscRegNoEffect(Context, context);
+ tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
setExceptionState(tc, 0x3);
// Set new PC
Addr HandlerBase;
// Offset 0x180 - General Exception Vector
- HandlerBase = vect() + tc->readMiscReg(EBase);
+ HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
setHandlerPC(HandlerBase, tc);
}
@@ -304,12 +304,12 @@
{
DPRINTF(MipsPRA, "%s encountered.\n", name());
setExceptionState(tc, 0x4);
- tc->setMiscRegNoEffect(BadVAddr, badVAddr);
+ tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
// Set new PC
Addr HandlerBase;
// Offset 0x180 - General Exception Vector
- HandlerBase = vect() + tc->readMiscReg(EBase);
+ HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
setHandlerPC(HandlerBase, tc);
}
@@ -318,51 +318,51 @@
{
DPRINTF(MipsPRA, "%s encountered.\n", name());
setExceptionState(tc, 0x2);
- tc->setMiscRegNoEffect(BadVAddr, badVAddr);
- EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+ tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
+ EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
entryHi.asid = entryHiAsid;
entryHi.vpn2 = entryHiVPN2;
entryHi.vpn2x = entryHiVPN2X;
- tc->setMiscRegNoEffect(EntryHi, entryHi);
+ tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
- ContextReg context = tc->readMiscReg(Context);
+ ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
context.badVPN2 = contextBadVPN2;
- tc->setMiscRegNoEffect(Context, context);
+ tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
// Set new PC
Addr HandlerBase;
// Offset 0x180 - General Exception Vector
- HandlerBase = vect() + tc->readMiscReg(EBase);
+ HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
setHandlerPC(HandlerBase,tc);
DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n",
- HandlerBase, tc->readMiscReg(EPC));
+ HandlerBase, tc->readMiscReg(MISCREG_EPC));
}
void
ItbRefillFault::invoke(ThreadContext *tc)
{
- DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), badVAddr);
+ DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
Addr HandlerBase;
- tc->setMiscRegNoEffect(BadVAddr, badVAddr);
- EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+ tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
+ EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
entryHi.asid = entryHiAsid;
entryHi.vpn2 = entryHiVPN2;
entryHi.vpn2x = entryHiVPN2X;
- tc->setMiscRegNoEffect(EntryHi, entryHi);
- ContextReg context = tc->readMiscReg(Context);
+ tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
+ ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
context.badVPN2 = contextBadVPN2;
- tc->setMiscRegNoEffect(Context, context);
+ tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
- StatusReg status = tc->readMiscReg(Status);
+ StatusReg status = tc->readMiscReg(MISCREG_STATUS);
// Since handler depends on EXL bit, must check EXL bit before setting it!!
// See MIPS ARM Vol 3, Revision 2, Page 38
if (status.exl == 1) {
// Offset 0x180 - General Exception Vector
- HandlerBase = vect() + tc->readMiscReg(EBase);
+ HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
} else {
// Offset 0x000
- HandlerBase = tc->readMiscReg(EBase);
+ HandlerBase = tc->readMiscReg(MISCREG_EBASE);
}
setExceptionState(tc, 0x2);
@@ -375,26 +375,26 @@
// Set new PC
DPRINTF(MipsPRA, "%s encountered.\n", name());
Addr HandlerBase;
- tc->setMiscRegNoEffect(BadVAddr, badVAddr);
- EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+ tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
+ EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
entryHi.asid = entryHiAsid;
entryHi.vpn2 = entryHiVPN2;
entryHi.vpn2x = entryHiVPN2X;
- tc->setMiscRegNoEffect(EntryHi, entryHi);
+ tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
- ContextReg context = tc->readMiscReg(Context);
+ ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
context.badVPN2 = contextBadVPN2;
- tc->setMiscRegNoEffect(Context, context);
+ tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
- StatusReg status = tc->readMiscReg(Status);
+ StatusReg status = tc->readMiscReg(MISCREG_STATUS);
// Since handler depends on EXL bit, must check EXL bit before setting it!!
// See MIPS ARM Vol 3, Revision 2, Page 38
if (status.exl) {
// Offset 0x180 - General Exception Vector
- HandlerBase = vect() + tc->readMiscReg(EBase);
+ HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
} else {
// Offset 0x000
- HandlerBase = tc->readMiscReg(EBase);
+ HandlerBase = tc->readMiscReg(MISCREG_EBASE);
}
setExceptionState(tc, 0x3);
@@ -406,21 +406,21 @@
TLBModifiedFault::invoke(ThreadContext *tc)
{
DPRINTF(MipsPRA, "%s encountered.\n", name());
- tc->setMiscRegNoEffect(BadVAddr, badVAddr);
- EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+ tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
+ EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
entryHi.asid = entryHiAsid;
entryHi.vpn2 = entryHiVPN2;
entryHi.vpn2x = entryHiVPN2X;
- tc->setMiscRegNoEffect(EntryHi, entryHi);
+ tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
- ContextReg context = tc->readMiscReg(Context);
+ ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
context.badVPN2 = contextBadVPN2;
- tc->setMiscRegNoEffect(Context, context);
+ tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
// Set new PC
Addr HandlerBase;
// Offset 0x180 - General Exception Vector
- HandlerBase = vect() + tc->readMiscReg(EBase);
+ HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
setExceptionState(tc, 0x1);
setHandlerPC(HandlerBase, tc);
@@ -435,7 +435,7 @@
// Set new PC
Addr HandlerBase;
// Offset 0x180 - General Exception Vector
- HandlerBase = vect() + tc->readMiscReg(EBase);
+ HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
setHandlerPC(HandlerBase, tc);
}
@@ -447,13 +447,13 @@
setExceptionState(tc, 0x0A);
Addr HandlerBase;
- CauseReg cause = tc->readMiscRegNoEffect(Cause);
+ CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
if (cause.iv) {
// Offset 200 for release 2
- HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(EBase);
+ HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
} else {
//Ofset at 180 for release 1
- HandlerBase = vect() + tc->readMiscRegNoEffect(EBase);
+ HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
}
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