changeset 5209002cb6d5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5209002cb6d5
description:
MIPS: Style/formatting sweep of the decoder itself.
diffstat:
1 file changed, 1406 insertions(+), 1004 deletions(-)
src/arch/mips/isa/decoder.isa | 2410 +++++++++++++++++++++++------------------
diffs (truncated from 3084 to 300 lines):
diff -r 31c067ae3331 -r 5209002cb6d5 src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa Tue Jul 21 23:38:26 2009 -0700
+++ b/src/arch/mips/isa/decoder.isa Wed Jul 22 01:51:10 2009 -0700
@@ -46,8 +46,12 @@
0x0: decode FUNCTION_LO {
0x1: decode MOVCI {
format BasicOp {
- 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd :
Rs; }});
- 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd :
Rs; }});
+ 0: movf({{
+ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs;
+ }});
+ 1: movt({{
+ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs;
+ }});
}
}
@@ -69,8 +73,11 @@
0x0:decode SRL {
0: srl({{ Rd = Rt.uw >> SA; }});
- //Hardcoded assuming 32-bit ISA, probably need
parameter here
- 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >>
SA);}});
+ //Hardcoded assuming 32-bit ISA,
+ //probably need parameter here
+ 1: rotr({{
+ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);
+ }});
}
}
@@ -93,8 +100,12 @@
0x6: decode SRLV {
0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
- //Hardcoded assuming 32-bit ISA, probably need
parameter here
- 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >>
Rs<4:0>);}});
+ //Hardcoded assuming 32-bit ISA,
+ //probably need parameter here
+ 1: rotrv({{
+ Rd = (Rt.uw << (32 - Rs<4:0>)) |
+ (Rt.uw >> Rs<4:0>);
+ }});
}
0x7: srav({{
@@ -102,14 +113,13 @@
uint32_t temp = Rt >> shift_amt;
- if ( (Rt & 0x80000000) > 0 ) {
- uint32_t mask = 0x80000000;
- for(int i=0; i < shift_amt; i++) {
- temp |= mask;
- mask = mask >> 1;
- }
+ if ((Rt & 0x80000000) > 0) {
+ uint32_t mask = 0x80000000;
+ for (int i = 0; i < shift_amt; i++) {
+ temp |= mask;
+ mask = mask >> 1;
}
-
+ }
Rd = temp;
}});
}
@@ -149,9 +159,7 @@
0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
#if FULL_SYSTEM
- 0x4: syscall({{
- fault = new SystemCallFault();
- }});
+ 0x4: syscall({{ fault = new SystemCallFault(); }});
#else
0x4: syscall({{ xc->syscall(R2); }},
IsSerializeAfter, IsNonSpeculative);
@@ -163,9 +171,11 @@
}
0x2: decode FUNCTION_LO {
- 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, IntMultOp,
IsIprAccess);
+ 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }},
+ IntMultOp, IsIprAccess);
0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
- 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, IntMultOp,
IsIprAccess);
+ 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }},
+ IntMultOp, IsIprAccess);
0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
}
@@ -176,16 +186,18 @@
}
format HiLoOp {
- 0x2: div({{ if (Rt.sd != 0) {
- HI0 = Rs.sd % Rt.sd;
- LO0 = Rs.sd / Rt.sd;
- }
+ 0x2: div({{
+ if (Rt.sd != 0) {
+ HI0 = Rs.sd % Rt.sd;
+ LO0 = Rs.sd / Rt.sd;
+ }
}}, IntDivOp);
- 0x3: divu({{ if (Rt.ud != 0) {
- HI0 = Rs.ud % Rt.ud;
- LO0 = Rs.ud / Rt.ud;
- }
+ 0x3: divu({{
+ if (Rt.ud != 0) {
+ HI0 = Rs.ud % Rt.ud;
+ LO0 = Rs.ud / Rt.ud;
+ }
}}, IntDivOp);
}
}
@@ -193,47 +205,51 @@
0x4: decode HINT {
0x0: decode FUNCTION_LO {
format IntOp {
- 0x0: add({{ /* More complicated since an ADD can cause
an arithmetic overflow exception */
- int64_t Src1 = Rs.sw;
- int64_t Src2 = Rt.sw;
- int64_t temp_result;
-#if FULL_SYSTEM
- if(((Src1 >> 31) & 1) == 1)
- Src1 |= 0x100000000LL;
+ 0x0: add({{
+ /* More complicated since an ADD can cause
+ an arithmetic overflow exception */
+ int64_t Src1 = Rs.sw;
+ int64_t Src2 = Rt.sw;
+ int64_t temp_result;
+#if FULL_SYSTEM
+ if (((Src1 >> 31) & 1) == 1)
+ Src1 |= 0x100000000LL;
#endif
- temp_result = Src1 + Src2;
-#if FULL_SYSTEM
- if(((temp_result >> 31) & 1) ==
((temp_result >> 32) & 1)){
+ temp_result = Src1 + Src2;
+#if FULL_SYSTEM
+ if (bits(temp_result, 31) ==
+ bits(temp_result, 32)) {
#endif
- Rd.sw = temp_result;
-#if FULL_SYSTEM
- } else{
- fault = new ArithmeticFault();
- }
+ Rd.sw = temp_result;
+#if FULL_SYSTEM
+ } else {
+ fault = new ArithmeticFault();
+ }
#endif
-
- }});
+ }});
0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
0x2: sub({{
- /* More complicated since an SUB can
cause an arithmetic overflow exception */
- int64_t Src1 = Rs.sw;
- int64_t Src2 = Rt.sw;
- int64_t temp_result = Src1 - Src2;
+ /* More complicated since an SUB can cause
+ an arithmetic overflow exception */
+ int64_t Src1 = Rs.sw;
+ int64_t Src2 = Rt.sw;
+ int64_t temp_result = Src1 - Src2;
#if FULL_SYSTEM
- if(((temp_result >> 31) & 1) ==
((temp_result>>32) & 1)){
+ if (bits(temp_result, 31) ==
+ bits(temp_result, 32)) {
#endif
- Rd.sw = temp_result;
+ Rd.sw = temp_result;
#if FULL_SYSTEM
- } else{
- fault = new ArithmeticFault();
- }
+ } else {
+ fault = new ArithmeticFault();
+ }
#endif
- }});
- 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
- 0x4: and({{ Rd = Rs & Rt;}});
- 0x5: or({{ Rd = Rs | Rt;}});
- 0x6: xor({{ Rd = Rs ^ Rt;}});
- 0x7: nor({{ Rd = ~(Rs | Rt);}});
+ }});
+ 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw; }});
+ 0x4: and({{ Rd = Rs & Rt; }});
+ 0x5: or({{ Rd = Rs | Rt; }});
+ 0x6: xor({{ Rd = Rs ^ Rt; }});
+ 0x7: nor({{ Rd = ~(Rs | Rt); }});
}
}
}
@@ -241,8 +257,8 @@
0x5: decode HINT {
0x0: decode FUNCTION_LO {
format IntOp{
- 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
- 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
+ 0x2: slt({{ Rd.sw = (Rs.sw < Rt.sw) ? 1 : 0 }});
+ 0x3: sltu({{ Rd.uw = (Rs.uw < Rt.uw) ? 1 : 0 }});
}
}
}
@@ -272,11 +288,15 @@
0x1: decode REGIMM_LO {
format TrapImm {
0x0: tgei( {{ cond = (Rs.sw >= (int16_t)INTIMM); }});
- 0x1: tgeiu({{ cond = (Rs.uw >=
(uint32_t)((int32_t)((int16_t)INTIMM))); }});
+ 0x1: tgeiu({{
+ cond = (Rs.uw >= (uint32_t)(int32_t)(int16_t)INTIMM);
+ }});
0x2: tlti( {{ cond = (Rs.sw < (int16_t)INTIMM); }});
- 0x3: tltiu({{ cond = (Rs.uw <
(uint32_t)((int32_t)((int16_t)INTIMM))); }});
- 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM);}});
- 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM);}});
+ 0x3: tltiu({{
+ cond = (Rs.uw < (uint32_t)(int32_t)(int16_t)INTIMM);
+ }});
+ 0x4: teqi( {{ cond = (Rs.sw == (int16_t)INTIMM); }});
+ 0x6: tnei( {{ cond = (Rs.sw != (int16_t)INTIMM); }});
}
}
@@ -293,7 +313,8 @@
}
0x3: decode REGIMM_LO {
- // from Table 5-4 MIPS32 REGIMM Encoding of rt Field (DSP ASE
MANUAL)
+ // from Table 5-4 MIPS32 REGIMM Encoding of rt Field
+ // (DSP ASE MANUAL)
0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }});
format WarnUnimpl {
0x7: synci();
@@ -302,9 +323,9 @@
}
format Jump {
- 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
- 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall,
- Link);
+ 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }});
+ 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},
+ IsCall, Link);
}
format Branch {
@@ -321,41 +342,47 @@
0x1: decode OPCODE_LO {
format IntImmOp {
0x0: addi({{
- int64_t Src1 = Rs.sw;
- int64_t Src2 = imm;
- int64_t temp_result;
+ int64_t Src1 = Rs.sw;
+ int64_t Src2 = imm;
+ int64_t temp_result;
#if FULL_SYSTEM
- if(((Src1 >> 31) & 1) == 1)
- Src1 |= 0x100000000LL;
+ if (((Src1 >> 31) & 1) == 1)
+ Src1 |= 0x100000000LL;
#endif
- temp_result = Src1 + Src2;
+ temp_result = Src1 + Src2;
#if FULL_SYSTEM
- if(((temp_result >> 31) & 1) == ((temp_result >> 32)
& 1)){
+ if (bits(temp_result, 31) == bits(temp_result, 32)) {
#endif
- Rt.sw = temp_result;
+ Rt.sw = temp_result;
#if FULL_SYSTEM
- } else{
- fault = new ArithmeticFault();
- }
+ } else {
+ fault = new ArithmeticFault();
+ }
#endif
- }});
- 0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
- 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
+ }});
+ 0x1: addiu({{ Rt.sw = Rs.sw + imm; }});
+ 0x2: slti({{ Rt.sw = (Rs.sw < imm) ? 1 : 0 }});
//Edited to include MIPS AVP Pass/Fail instructions and
//default to the sltiu instruction
0x3: decode RS_RT_INTIMM {
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