changeset 8e72cf8196cc in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8e72cf8196cc
description:
X86: Fix the sar carry flag.
diffstat:
1 file changed, 5 insertions(+), 1 deletion(-)
src/arch/x86/isa/microops/regop.isa | 6 +++++-
diffs (17 lines):
diff -r fa4e81c993d0 -r 8e72cf8196cc src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Wed Aug 05 02:57:47 2009 -0700
+++ b/src/arch/x86/isa/microops/regop.isa Wed Aug 05 02:58:03 2009 -0700
@@ -711,8 +711,12 @@
//worry about setting them.
ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
//If some combination of the CF bits need to be set, set them.
- if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
+ uint8_t effectiveShift =
+ (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8);
+ if ((ext & (CFBit | ECFBit)) &&
+ bits(SrcReg1, effectiveShift - 1)) {
ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
+ }
//Use the regular mechanisms to calculate the other flags.
ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit |
OFBit),
DestReg, psrc1, op2);
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