changeset a32abe4e17e1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a32abe4e17e1
description:
X86: Set the flags on a rotate right instruction.
diffstat:
1 file changed, 9 insertions(+), 9 deletions(-)
src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py | 18
+++++-----
diffs (74 lines):
diff -r eebbe9f1bf10 -r a32abe4e17e1
src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py
--- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py Wed Aug
05 02:59:25 2009 -0700
+++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py Wed Aug
05 02:59:39 2009 -0700
@@ -116,13 +116,13 @@
def macroop ROR_R_I
{
- rori reg, reg, imm
+ rori reg, reg, imm, flags=(OF,CF)
};
def macroop ROR_M_I
{
ldst t1, seg, sib, disp
- rori t1, t1, imm
+ rori t1, t1, imm, flags=(OF,CF)
st t1, seg, sib, disp
};
@@ -130,19 +130,19 @@
{
rdip t7
ldst t1, seg, riprel, disp
- rori t1, t1, imm
+ rori t1, t1, imm, flags=(OF,CF)
st t1, seg, riprel, disp
};
def macroop ROR_1_R
{
- rori reg, reg, 1
+ rori reg, reg, 1, flags=(OF,CF)
};
def macroop ROR_1_M
{
ldst t1, seg, sib, disp
- rori t1, t1, 1
+ rori t1, t1, 1, flags=(OF,CF)
st t1, seg, sib, disp
};
@@ -150,19 +150,19 @@
{
rdip t7
ldst t1, seg, riprel, disp
- rori t1, t1, 1
+ rori t1, t1, 1, flags=(OF,CF)
st t1, seg, riprel, disp
};
def macroop ROR_R_R
{
- ror reg, reg, regm
+ ror reg, reg, regm, flags=(OF,CF)
};
def macroop ROR_M_R
{
ldst t1, seg, sib, disp
- ror t1, t1, reg
+ ror t1, t1, reg, flags=(OF,CF)
st t1, seg, sib, disp
};
@@ -170,7 +170,7 @@
{
rdip t7
ldst t1, seg, riprel, disp
- ror t1, t1, reg
+ ror t1, t1, reg, flags=(OF,CF)
st t1, seg, riprel, disp
};
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