changeset 5670eee2a866 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5670eee2a866
description:
slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized
controllers
This changeset contains a lot of different changes that are too
mingled to separate. They are:
1. Added MOESI_CMP_directory
I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller. I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.
2. DMA Sequencer uses a generic SequencerMsg
I will eventually make the cache Sequencer use this type as well. It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.
3. Parameterized Controllers
SLICC controllers can now take custom parameters to use for mapping,
latencies, etc. Currently, only int parameters are supported.
diffstat:
47 files changed, 1187 insertions(+), 1068 deletions(-)
src/mem/gems_common/Map.hh | 2
src/mem/protocol/MI_example-cache.sm | 15
src/mem/protocol/MI_example-dir.sm | 44
src/mem/protocol/MI_example-dma.sm | 24
src/mem/protocol/MI_example-msg.sm | 1
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 137 +-
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 86 -
src/mem/protocol/MOESI_CMP_directory-dir.sm | 313 +++++
src/mem/protocol/MOESI_CMP_directory-dma.sm | 267 ++++
src/mem/protocol/MOESI_CMP_directory-msg.sm | 35
src/mem/protocol/MOESI_CMP_directory.slicc | 1
src/mem/protocol/MOESI_CMP_directory_m-dir.sm | 652 ------------
src/mem/protocol/MOESI_CMP_directory_m.slicc | 5
src/mem/protocol/RubySlicc_ComponentMapping.sm | 7
src/mem/protocol/RubySlicc_Exports.sm | 33
src/mem/protocol/RubySlicc_Profiler.sm | 2
src/mem/protocol/RubySlicc_Types.sm | 5
src/mem/protocol/RubySlicc_Util.sm | 2
src/mem/ruby/config/MI_example-homogeneous.rb | 15
src/mem/ruby/config/MI_example.rb | 35
src/mem/ruby/config/MOESI_CMP_directory.rb | 79 +
src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb | 98 +
src/mem/ruby/config/cfg.rb | 81 -
src/mem/ruby/config/defaults.rb | 50
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh | 8
src/mem/ruby/slicc_interface/RubySlicc_Util.hh | 5
src/mem/ruby/system/DMASequencer.cc | 34
src/mem/ruby/system/DirectoryMemory.cc | 6
src/mem/ruby/system/DirectoryMemory.hh | 6
src/mem/ruby/system/PerfectCacheMemory.hh | 14
src/mem/ruby/system/System.hh | 3
src/mem/ruby/system/TimerTable.cc | 4
src/mem/ruby/system/TimerTable.hh | 4
src/mem/slicc/ast/AST.hh | 14
src/mem/slicc/ast/ActionDeclAST.cc | 2
src/mem/slicc/ast/ActionDeclAST.hh | 3
src/mem/slicc/ast/EnqueueStatementAST.cc | 9
src/mem/slicc/ast/FormalParamAST.cc | 11
src/mem/slicc/ast/FormalParamAST.hh | 6
src/mem/slicc/ast/FuncDeclAST.cc | 1
src/mem/slicc/ast/FuncDeclAST.hh | 3
src/mem/slicc/ast/MachineAST.cc | 9
src/mem/slicc/ast/MachineAST.hh | 8
src/mem/slicc/parser/parser.py | 28
src/mem/slicc/parser/parser.yy | 10
src/mem/slicc/symbols/StateMachine.cc | 73 -
src/mem/slicc/symbols/StateMachine.hh | 5
diffs (truncated from 3945 to 300 lines):
diff -r 4e66dd2decd7 -r 5670eee2a866 src/mem/gems_common/Map.hh
--- a/src/mem/gems_common/Map.hh Tue Aug 04 12:42:45 2009 -0500
+++ b/src/mem/gems_common/Map.hh Tue Aug 04 12:52:52 2009 -0500
@@ -93,6 +93,8 @@
template <class KEY_TYPE, class VALUE_TYPE>
VALUE_TYPE& Map<KEY_TYPE, VALUE_TYPE>::lookup(const KEY_TYPE& key) const
{
+ if (!exist(key))
+ cerr << *this << " is looking for " << key << endl;
assert(exist(key));
return m_map[key];
}
diff -r 4e66dd2decd7 -r 5670eee2a866 src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm Tue Aug 04 12:42:45 2009 -0500
+++ b/src/mem/protocol/MI_example-cache.sm Tue Aug 04 12:52:52 2009 -0500
@@ -1,5 +1,8 @@
-machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY
LATENCY_ISSUE_LATENCY {
+machine(L1Cache, "MI Example L1 Cache")
+: int cache_response_latency,
+ int issue_latency
+{
// NETWORK BUFFERS
MessageBuffer requestFromCache, network="To", virtual_network="0",
ordered="true";
@@ -188,8 +191,8 @@
// ACTIONS
action(a_issueRequest, "a", desc="Issue a request") {
- enqueue(requestNetwork_out, RequestMsg, latency="ISSUE_LATENCY") {
- out_msg.Address := address;
+ enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
+ out_msg.Address := address;
out_msg.Type := CoherenceRequestType:GETX;
out_msg.Requestor := machineID;
out_msg.Destination.add(map_Address_to_Directory(address));
@@ -198,7 +201,7 @@
}
action(b_issuePUT, "b", desc="Issue a PUT request") {
- enqueue(requestNetwork_out, RequestMsg, latency="ISSUE_LATENCY") {
+ enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:PUTX;
out_msg.Requestor := machineID;
@@ -211,7 +214,7 @@
action(e_sendData, "e", desc="Send data from cache to requestor") {
peek(forwardRequestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg,
latency="CACHE_RESPONSE_LATENCY") {
+ enqueue(responseNetwork_out, ResponseMsg,
latency=cache_response_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
@@ -224,7 +227,7 @@
action(ee_sendDataFromTBE, "\e", desc="Send data from TBE to requestor") {
peek(forwardRequestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg,
latency="CACHE_RESPONSE_LATENCY") {
+ enqueue(responseNetwork_out, ResponseMsg,
latency=cache_response_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
diff -r 4e66dd2decd7 -r 5670eee2a866 src/mem/protocol/MI_example-dir.sm
--- a/src/mem/protocol/MI_example-dir.sm Tue Aug 04 12:42:45 2009 -0500
+++ b/src/mem/protocol/MI_example-dir.sm Tue Aug 04 12:52:52 2009 -0500
@@ -1,5 +1,7 @@
-machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY
LATENCY_DIRECTORY_LATENCY LATENCY_MEMORY_LATENCY {
+machine(Directory, "Directory protocol")
+: int directory_latency
+{
MessageBuffer forwardFromDir, network="To", virtual_network="2",
ordered="false";
MessageBuffer responseFromDir, network="To", virtual_network="1",
ordered="false";
@@ -65,9 +67,9 @@
// TBE entries for DMA requests
structure(TBE, desc="TBE entries for outstanding DMA requests") {
+ Address PhysicalAddress, desc="physical address";
State TBEState, desc="Transient State";
DataBlock DataBlk, desc="Data to be written (DMA write only)";
- int Offset, desc="...";
int Len, desc="...";
}
@@ -180,7 +182,7 @@
action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
peek(requestQueue_in, RequestMsg) {
- enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") {
+ enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:WB_ACK;
out_msg.Requestor := in_msg.Requestor;
@@ -192,7 +194,7 @@
action(l_sendWriteBackAck, "la", desc="Send writeback ack to requestor") {
peek(memQueue_in, MemoryMsg) {
- enqueue(forwardNetwork_out, RequestMsg, latency="TO_MEM_CTRL_LATENCY") {
+ enqueue(forwardNetwork_out, RequestMsg, latency="1") {
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:WB_ACK;
out_msg.Requestor := in_msg.OriginalRequestorMachId;
@@ -204,7 +206,7 @@
action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") {
peek(requestQueue_in, RequestMsg) {
- enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") {
+ enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:WB_NACK;
out_msg.Requestor := in_msg.Requestor;
@@ -240,7 +242,7 @@
action(d_sendData, "d", desc="Send data to requestor") {
peek(memQueue_in, MemoryMsg) {
- enqueue(responseNetwork_out, ResponseMsg, latency="TO_MEM_CTRL_LATENCY")
{
+ enqueue(responseNetwork_out, ResponseMsg, latency="1") {
out_msg.Address := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
@@ -265,7 +267,7 @@
action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from
directory") {
peek(memQueue_in, MemoryMsg) {
- enqueue(dmaResponseNetwork_out, DMAResponseMsg,
latency="MEMORY_LATENCY") {
+ enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
out_msg.PhysicalAddress := address;
out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:DATA;
@@ -280,7 +282,7 @@
action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from
incoming PUTX") {
peek(requestQueue_in, RequestMsg) {
- enqueue(dmaResponseNetwork_out, DMAResponseMsg,
latency="MEMORY_LATENCY") {
+ enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
out_msg.PhysicalAddress := address;
out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:DATA;
@@ -292,7 +294,7 @@
}
action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
- enqueue(dmaResponseNetwork_out, DMAResponseMsg,
latency="MEMORY_LATENCY") {
+ enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
out_msg.PhysicalAddress := address;
out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:ACK;
@@ -318,7 +320,7 @@
APPEND_TRANSITION_COMMENT(directory[in_msg.Address].Owner);
APPEND_TRANSITION_COMMENT("Req: ");
APPEND_TRANSITION_COMMENT(in_msg.Requestor);
- enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") {
+ enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
out_msg.Address := address;
out_msg.Type := in_msg.Type;
out_msg.Requestor := in_msg.Requestor;
@@ -330,7 +332,7 @@
action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
peek(dmaRequestQueue_in, DMARequestMsg) {
- enqueue(forwardNetwork_out, RequestMsg, latency="DIRECTORY_LATENCY") {
+ enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:INV;
out_msg.Requestor := machineID;
@@ -359,14 +361,14 @@
}
action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from
TBE") {
- directory[address].DataBlk.copyPartial(TBEs[address].DataBlk,
TBEs[address].Offset, TBEs[address].Len);
+ directory[address].DataBlk.copyPartial(TBEs[address].DataBlk,
addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
}
action(v_allocateTBE, "v", desc="Allocate TBE") {
peek(dmaRequestQueue_in, DMARequestMsg) {
TBEs.allocate(address);
TBEs[address].DataBlk := in_msg.DataBlk;
- TBEs[address].Offset := in_msg.Offset;
+ TBEs[address].PhysicalAddress := in_msg.PhysicalAddress;
TBEs[address].Len := in_msg.Len;
}
}
@@ -389,7 +391,7 @@
action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch
request") {
peek(requestQueue_in, RequestMsg) {
- enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") {
+ enqueue(memQueue_out, MemoryMsg, latency="1") {
out_msg.Address := address;
out_msg.Type := MemoryRequestType:MEMORY_READ;
out_msg.Sender := machineID;
@@ -403,7 +405,7 @@
action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch
request") {
peek(dmaRequestQueue_in, DMARequestMsg) {
- enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") {
+ enqueue(memQueue_out, MemoryMsg, latency="1") {
out_msg.Address := address;
out_msg.Type := MemoryRequestType:MEMORY_READ;
out_msg.Sender := machineID;
@@ -416,7 +418,7 @@
}
// action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback
request") {
// peek(dmaRequestQueue_in, DMARequestMsg) {
-// enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") {
+// enqueue(memQueue_out, MemoryMsg, latency="1") {
// out_msg.Address := address;
// out_msg.Type := MemoryRequestType:MEMORY_WB;
// out_msg.OriginalRequestorMachId := machineID;
@@ -431,12 +433,12 @@
action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip
writeback request") {
peek(dmaRequestQueue_in, DMARequestMsg) {
- enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") {
+ enqueue(memQueue_out, MemoryMsg, latency="1") {
out_msg.Address := address;
out_msg.Type := MemoryRequestType:MEMORY_WB;
//out_msg.OriginalRequestorMachId := machineID;
//out_msg.DataBlk := in_msg.DataBlk;
- out_msg.DataBlk.copyPartial(in_msg.DataBlk, in_msg.Offset, in_msg.Len);
+ out_msg.DataBlk.copyPartial(in_msg.DataBlk,
addressOffset(in_msg.PhysicalAddress), in_msg.Len);
out_msg.MessageSize := in_msg.MessageSize;
//out_msg.Prefetch := in_msg.Prefetch;
@@ -447,12 +449,12 @@
action(qw_queueMemoryWBRequest_partialTBE, "qwt", desc="Queue off-chip
writeback request") {
peek(requestQueue_in, RequestMsg) {
- enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") {
+ enqueue(memQueue_out, MemoryMsg, latency="1") {
out_msg.Address := address;
out_msg.Type := MemoryRequestType:MEMORY_WB;
out_msg.OriginalRequestorMachId := in_msg.Requestor;
//out_msg.DataBlk := in_msg.DataBlk;
- out_msg.DataBlk.copyPartial(TBEs[address].DataBlk,
TBEs[address].Offset, TBEs[address].Len);
+ out_msg.DataBlk.copyPartial(TBEs[address].DataBlk,
addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
out_msg.MessageSize := in_msg.MessageSize;
//out_msg.Prefetch := in_msg.Prefetch;
@@ -465,7 +467,7 @@
action(l_queueMemoryWBRequest, "lq", desc="Write PUTX data to memory") {
peek(requestQueue_in, RequestMsg) {
- enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") {
+ enqueue(memQueue_out, MemoryMsg, latency="1") {
out_msg.Address := address;
out_msg.Type := MemoryRequestType:MEMORY_WB;
out_msg.OriginalRequestorMachId := in_msg.Requestor;
diff -r 4e66dd2decd7 -r 5670eee2a866 src/mem/protocol/MI_example-dma.sm
--- a/src/mem/protocol/MI_example-dma.sm Tue Aug 04 12:42:45 2009 -0500
+++ b/src/mem/protocol/MI_example-dma.sm Tue Aug 04 12:52:52 2009 -0500
@@ -1,5 +1,7 @@
-machine(DMA, "DMA Controller") {
+machine(DMA, "DMA Controller")
+: int request_latency
+{
MessageBuffer responseFromDir, network="From", virtual_network="4",
ordered="true", no_vector="true";
MessageBuffer reqToDirectory, network="To", virtual_network="5",
ordered="false", no_vector="true";
@@ -35,12 +37,12 @@
out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
- in_port(dmaRequestQueue_in, DMARequestMsg, mandatoryQueue, desc="...") {
+ in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
if (dmaRequestQueue_in.isReady()) {
- peek(dmaRequestQueue_in, DMARequestMsg) {
- if (in_msg.Type == DMARequestType:READ ) {
+ peek(dmaRequestQueue_in, SequencerMsg) {
+ if (in_msg.Type == SequencerRequestType:LD ) {
trigger(Event:ReadRequest, in_msg.LineAddress);
- } else if (in_msg.Type == DMARequestType:WRITE) {
+ } else if (in_msg.Type == SequencerRequestType:ST) {
trigger(Event:WriteRequest, in_msg.LineAddress);
} else {
error("Invalid request type");
@@ -64,9 +66,9 @@
}
action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
- peek(dmaRequestQueue_in, DMARequestMsg) {
- enqueue(reqToDirectory_out, DMARequestMsg) {
- out_msg.PhysicalAddress := address;
+ peek(dmaRequestQueue_in, SequencerMsg) {
+ enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) {
+ out_msg.PhysicalAddress := in_msg.PhysicalAddress;
out_msg.LineAddress := in_msg.LineAddress;
out_msg.Type := DMARequestType:READ;
out_msg.DataBlk := in_msg.DataBlk;
@@ -78,9 +80,9 @@
}
action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
- peek(dmaRequestQueue_in, DMARequestMsg) {
- enqueue(reqToDirectory_out, DMARequestMsg) {
- out_msg.PhysicalAddress := address;
+ peek(dmaRequestQueue_in, SequencerMsg) {
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