changeset 26abdfe2d980 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=26abdfe2d980
description:
ruby: made mapAddressToRange based off a bit count
diffstat:
3 files changed, 20 insertions(+), 19 deletions(-)
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 30 ++++++------
src/mem/ruby/config/MOESI_CMP_directory.rb | 3 -
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh | 6 +-
diffs (175 lines):
diff -r 5670eee2a866 -r 26abdfe2d980
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Tue Aug 04 12:52:52
2009 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Tue Aug 04 23:05:37
2009 -0500
@@ -35,7 +35,7 @@
machine(L1Cache, "Directory protocol")
: int request_latency,
int l2_select_low_bit,
- int l2_select_high_bit
+ int l2_select_num_bits
{
// NODE L1 CACHE
@@ -412,7 +412,7 @@
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address,
MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.MessageSize := MessageSizeType:Request_Control;
out_msg.AccessMode := in_msg.AccessMode;
out_msg.Prefetch := in_msg.Prefetch;
@@ -427,7 +427,7 @@
out_msg.Type := CoherenceRequestType:GETX;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address,
MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.MessageSize := MessageSizeType:Request_Control;
out_msg.AccessMode := in_msg.AccessMode;
out_msg.Prefetch := in_msg.Prefetch;
@@ -442,7 +442,7 @@
out_msg.Type := CoherenceRequestType:PUTX;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.MessageSize := MessageSizeType:Writeback_Control;
}
}
@@ -454,7 +454,7 @@
out_msg.Type := CoherenceRequestType:PUTO;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.MessageSize := MessageSizeType:Writeback_Control;
}
}
@@ -466,7 +466,7 @@
out_msg.Type := CoherenceRequestType:PUTS;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.MessageSize := MessageSizeType:Writeback_Control;
}
}
@@ -479,7 +479,7 @@
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address,
MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.DataBlk := getCacheEntry(address).DataBlk;
// out_msg.Dirty := getCacheEntry(address).Dirty;
out_msg.Dirty := false;
@@ -512,7 +512,7 @@
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.DataBlk := getCacheEntry(address).DataBlk;
out_msg.Dirty := getCacheEntry(address).Dirty;
out_msg.Acks := 0; // irrelevant
@@ -530,7 +530,7 @@
out_msg.Sender := machineID;
out_msg.SenderMachine := MachineType:L1Cache;
out_msg.Destination.add(mapAddressToRange(address,
MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.DataBlk := getCacheEntry(address).DataBlk;
out_msg.Dirty := getCacheEntry(address).Dirty;
out_msg.Acks := in_msg.Acks;
@@ -575,7 +575,7 @@
out_msg.Sender := machineID;
out_msg.SenderMachine := MachineType:L1Cache;
out_msg.Destination.add(mapAddressToRange(address,
MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.Acks := 0 - 1; // -1
out_msg.MessageSize := MessageSizeType:Response_Control;
}
@@ -589,7 +589,7 @@
out_msg.Type := CoherenceResponseType:UNBLOCK;
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.MessageSize := MessageSizeType:Unblock_Control;
}
}
@@ -600,7 +600,7 @@
out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.MessageSize := MessageSizeType:Unblock_Control;
}
}
@@ -692,7 +692,7 @@
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address,
MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.DataBlk := TBEs[address].DataBlk;
// out_msg.Dirty := TBEs[address].Dirty;
out_msg.Dirty := false;
@@ -723,7 +723,7 @@
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address,
MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.DataBlk := TBEs[address].DataBlk;
out_msg.Dirty := TBEs[address].Dirty;
out_msg.Acks := in_msg.Acks;
@@ -741,7 +741,7 @@
out_msg.Sender := machineID;
out_msg.SenderMachine := MachineType:L1Cache;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit,
l2_select_high_bit));
+ l2_select_low_bit,
l2_select_num_bits));
out_msg.Dirty := TBEs[address].Dirty;
if (TBEs[address].Dirty) {
out_msg.Type := CoherenceResponseType:WRITEBACK_DIRTY_DATA;
diff -r 5670eee2a866 -r 26abdfe2d980 src/mem/ruby/config/MOESI_CMP_directory.rb
--- a/src/mem/ruby/config/MOESI_CMP_directory.rb Tue Aug 04 12:52:52
2009 -0500
+++ b/src/mem/ruby/config/MOESI_CMP_directory.rb Tue Aug 04 23:05:37
2009 -0500
@@ -26,14 +26,13 @@
num_block_bits = log_int(RubySystem.block_size_bytes)
l2_select_low_bit = num_block_bits
- l2_select_high_bit = num_block_bits + num_select_bits - 1
vec = super()
vec += " icache " + @icache.obj_name
vec += " dcache " + @dcache.obj_name
vec += " request_latency "+request_latency().to_s
vec += " l2_select_low_bit " + l2_select_low_bit.to_s
- vec += " l2_select_high_bit " + l2_select_high_bit.to_s
+ vec += " l2_select_num_bits " + num_select_bits.to_s
return vec
end
end
diff -r 5670eee2a866 -r 26abdfe2d980
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh Tue Aug
04 12:52:52 2009 -0500
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh Tue Aug
04 23:05:37 2009 -0500
@@ -86,10 +86,12 @@
}
inline
-MachineID mapAddressToRange(const Address & addr, MachineType type, int
low_bit, int high_bit)
+MachineID mapAddressToRange(const Address & addr, MachineType type, int
low_bit, int num_bits)
{
MachineID mach = {type, 0};
- mach.num = addr.bitSelect(low_bit, high_bit);
+ if (num_bits == 0)
+ return mach;
+ mach.num = addr.bitSelect(low_bit, low_bit+num_bits-1);
return mach;
}
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