Yes, x87 was superceded by 3dNow! and MMX, those in turn were superceded by SSE, and it wouldn't surprise me to see some new acronym come in and replace SSE. It hasn't taken any extrordinary effort to support both of the newer extensions since they're both SIMD, they both can be looked at as operating on 64 bit registers if you squint, and they have similar instructions. X87 is a bit tougher since it's a lot more different from those two as they are from each other. After working on this a bit, I'm planning to mostly separate out x87 and support it with its own microops. That would be roughly equivalent to running it in a special legacy block of logic that sits off the main data path, something I believe (according to PTLSim's manual) some Intel CPUs do.
Gabe Quoting Lisa Hsu <[email protected]>: > Just an FYI, I don't believe 3dNow! is supported anymore; at least, Rev 3.14 > of the 1st volume says: > > "AMD no longer recommends the use of 3DNow! insts, which have been > superceded by their more efficient 128-bit media counterparts." > > So I wouldn't do anything special to support them. > > Lisa > > On Sat, Aug 8, 2009 at 4:30 PM, Gabe Black <[email protected]> wrote: > >> I've gone through Rev 3.07 of fourth volume of AMD's manuals which >> describes all the 128 bit media instructions that were available at the >> time of that revision. In other words, I looked at all of the fairly >> recent SSE instructions. I'm not sure exactly what it excludes, but I >> saw SSE2 in there for sure. In any case, I've come up with a potential >> set of microops that will hopefully support all of these instructions. >> Ideally these will also support the older MMX/3dNow! instructions and >> maybe even x87, but I haven't made any attempt to ensure that. I realize >> it's not likely that anyone will know SSE so well off hand that they can >> point out very specific defects, but any general comments are also >> welcome. Also, I'm learning as I go, so please bring up anything that >> looks factually wrong. >> >> Each instruction will have a field that describes the width for its >> input data and output data. I'm pretty sure I'll have a bit that selects >> scalar or vector mode. I'd also like to have a general index/mask field >> that selects elements of a vector or the position in an input operand >> for scalar operations, but I'm not quite sure how that will work yet. >> >> These instructions will all work on "floating point" registers in M5's >> sense of the word. When doing integer operations, the "bits" version of >> the register will be used. That allows freely mixing MMX/XMM register >> accesses for integer and floating point computation which is how SSE and >> MMX/3dNow! work. I'm going to break each XMM register into two 64 bit >> halves and operate on them separately. That works in 99% of >> instructions, but there are I think 3 shift instructions that manipulate >> the whole 128 bits at a time. I'm not quite sure what I'm going to do >> for those yet, but I may set up something like I did for the regular >> SHLD and SHRD instructions. >> >> I'm planning on having 4 64 bit micro fp registers which will be >> generally available across all the media/FP instructions. In the future >> that may go up for things like x87's crazy trigonometric functions. In >> those cases I'd also potentially need to decide how to handle (or not >> handle) 80 bit floating point computation. >> >> Floating point: >> Add >> Subtract >> Compare (ordered or unordered) and write the result to RFLAGS. >> Compare (ordered and unordered?) and write the results to the floating >> point flags. >> Compare and write all 1s or 0s to a register. This could be considered >> integer too. >> Divide >> Max >> Min >> Multiply >> Reciprocate >> Square root >> >> Logic: >> Negate bits, may do with xor >> And >> Or >> Xor >> >> Integer: >> Add (unsaturated, unsigned saturated, signed saturated) >> Subtract (unsaturated, unsigned saturated, signed saturated) >> Average, may do this with other ops. >> Min (signed or unsigned) >> Max (signed or unsigned) >> Mul (signed or unsigned) >> Absolute differences >> Left shift >> Right shift logical >> Right shift arithmetic >> >> Moving: >> Shuffle >> Pack - shrink elements in a vector >> Unpack - widen elements in a vector >> Move from float register to GPR >> Move from GPR to float register >> Mux between two sources >> >> Conversion: >> Float to float >> Int to int >> Float to int (truncating, normal(?)) >> Int to float >> >> >> Gabe >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> >> > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
