changeset 82d1d4d217e4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=82d1d4d217e4
description:
X86: Implement STMXCSR.
diffstat:
2 files changed, 11 insertions(+), 2 deletions(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa
| 2 -
src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
| 11 +++++++++-
diffs (32 lines):
diff -r 4903cea6a8c2 -r 82d1d4d217e4
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Mon Aug 17 20:25:13
2009 -0700
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Mon Aug 17 20:25:13
2009 -0700
@@ -829,7 +829,7 @@
0x0: fxsave();
0x1: fxrstor();
0x2: ldmxcsr();
- 0x3: stmxcsr();
+ 0x3: Inst::STMXCSR(Md);
0x4: Inst::UD2();
0x5: decode MODRM_MOD {
0x3: BasicOperate::LFENCE(
diff -r 4903cea6a8c2 -r 82d1d4d217e4
src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
---
a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
Mon Aug 17 20:25:13 2009 -0700
+++
b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
Mon Aug 17 20:25:13 2009 -0700
@@ -54,6 +54,15 @@
# Authors: Gabe Black
microcode = '''
-# STMXCSR
+def macroop STMXCSR_M {
+ rdval t1, "InstRegIndex(MISCREG_MXCSR)"
+ st t1, seg, sib, disp
+};
+
+def macroop STMXCSR_P {
+ rdval t1, "InstRegIndex(MISCREG_MXCSR)"
+ rdip t7
+ st t1, seg, riprel, disp
+};
# LDMXCSR
'''
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