changeset a578850e7524 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a578850e7524
description:
X86: Implement LDMXCSR.
diffstat:
2 files changed, 12 insertions(+), 2 deletions(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa
| 2 -
src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
| 12 +++++++++-
diffs (32 lines):
diff -r 82d1d4d217e4 -r a578850e7524
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Mon Aug 17 20:25:13
2009 -0700
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Mon Aug 17 20:25:14
2009 -0700
@@ -828,7 +828,7 @@
0x6: decode MODRM_REG {
0x0: fxsave();
0x1: fxrstor();
- 0x2: ldmxcsr();
+ 0x2: Inst::LDMXCSR(Md);
0x3: Inst::STMXCSR(Md);
0x4: Inst::UD2();
0x5: decode MODRM_MOD {
diff -r 82d1d4d217e4 -r a578850e7524
src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
---
a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
Mon Aug 17 20:25:13 2009 -0700
+++
b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
Mon Aug 17 20:25:14 2009 -0700
@@ -64,5 +64,15 @@
rdip t7
st t1, seg, riprel, disp
};
-# LDMXCSR
+
+def macroop LDMXCSR_M {
+ ld t1, seg, sib, disp
+ wrval "InstRegIndex(MISCREG_MXCSR)", t1
+};
+
+def macroop LDMXCSR_P {
+ rdip t7
+ ld t1, seg, riprel, disp
+ wrval "InstRegIndex(MISCREG_MXCSR)", t1
+};
'''
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
