changeset cc03c3761eb2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cc03c3761eb2
description:
X86: Initialize the MXCSR in SE mode.
diffstat:
1 file changed, 4 insertions(+)
src/arch/x86/process.cc | 4 ++++
diffs (21 lines):
diff -r 6d1f74b21533 -r cc03c3761eb2 src/arch/x86/process.cc
--- a/src/arch/x86/process.cc Mon Aug 17 20:25:14 2009 -0700
+++ b/src/arch/x86/process.cc Mon Aug 17 20:25:14 2009 -0700
@@ -270,6 +270,8 @@
// setting it to one.
cr0.pe = 1; // We're definitely in protected mode.
tc->setMiscReg(MISCREG_CR0, cr0);
+
+ tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
}
}
@@ -390,6 +392,8 @@
// setting it to one.
cr0.pe = 1; // We're definitely in protected mode.
tc->setMiscReg(MISCREG_CR0, cr0);
+
+ tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
}
}
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
