Hi Korey, I just found out that the inorder-timing cpu (for ALPHA ISA in SE mode) is not able to simulate two workloads of the "hello" binary on a uniprocessor. It errors out saying that the simulation limit is reached.
I ran a trace (--trace-flags=Exec,Registers,GDBAll,MemoryAccess,InOrderCPUAll) and the CPU seems to be put to sleep right before the simulation errors out. 5000: system.cpu: Activity: 0 5000: system.cpu: No activity left! 5000: system.cpu: sleeping CPU. 5500: CacheUnitEvent: Waking up from TLB Miss caused by [sn:1]. 5500: system.cpu.stage-0: [tid:0]: Clearing stall by system.cpu.icache_port. 5500: system.cpu.stage-0: [tid:0]: There are no remaining resource stalls. Could you give me any pointers to debug this? regards, Soumyaroop. -- Soumyaroop Roy Ph.D. Candidate Department of Computer Science and Engineering University of South Florida, Tampa http://www.csee.usf.edu/~sroy <http://www.csee.usf.edu/%7Esroy>
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