changeset 57fba079b7ff in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=57fba079b7ff
description:
X86: Fix setting the busy bit in the task descriptor in LTR.
diffstat:
1 file changed, 6 insertions(+), 3 deletions(-)
src/arch/x86/isa/insts/system/segmentation.py | 9 ++++++---
diffs (33 lines):
diff -r 0f7957bb4450 -r 57fba079b7ff
src/arch/x86/isa/insts/system/segmentation.py
--- a/src/arch/x86/isa/insts/system/segmentation.py Wed Sep 16 09:47:38
2009 -0400
+++ b/src/arch/x86/isa/insts/system/segmentation.py Wed Sep 16 19:28:01
2009 -0700
@@ -179,7 +179,8 @@
wrdh t3, t1, t2
wrdl tr, t1, reg
wrbase tr, t3, dataSize=8
- ori t1, t1, (1 << 9)
+ limm t5, (1 << 9)
+ or t1, t1, t5
st t1, tsg, [8, t4, t0], dataSize=8
};
@@ -195,7 +196,8 @@
wrdh t3, t1, t2
wrdl tr, t1, t5
wrbase tr, t3, dataSize=8
- ori t1, t1, (1 << 9)
+ limm t5, (1 << 9)
+ or t1, t1, t5
st t1, tsg, [8, t4, t0], dataSize=8
};
@@ -212,7 +214,8 @@
wrdh t3, t1, t2
wrdl tr, t1, t5
wrbase tr, t3, dataSize=8
- ori t1, t1, (1 << 9)
+ limm t5, (1 << 9)
+ or t1, t1, t5
st t1, tsg, [8, t4, t0], dataSize=8
};
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