# HG changeset patch
# User Korey Sewell <[email protected]>
# Date 1254427252 14400
# Node ID b4106897b3d7191734e6c999dff8c980a713021d
# Parent 10f28313968a81a4ae5e149d4c30f0c463e3d0de
inorder: switch out buffer
add buffer for instructions to switch out to in a pipeline stage
can't squash the instruction and remove the pipeline so we kind of need
to 'suspend' an instruction at the stage while the memory stall resolves
for the switch on cache miss model
diff --git a/src/cpu/inorder/pipeline_stage.cc
b/src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -43,6 +43,9 @@
stageBufferMax(ThePipeline::interStageBuffSize[stage_num]),
prevStageValid(false), nextStageValid(false)
{
+ switchedOutBuffer.resize(ThePipeline::MaxThreads);
+ switchedOutValid.resize(ThePipeline::MaxThreads);
+
init(params);
}
diff --git a/src/cpu/inorder/pipeline_stage.hh
b/src/cpu/inorder/pipeline_stage.hh
--- a/src/cpu/inorder/pipeline_stage.hh
+++ b/src/cpu/inorder/pipeline_stage.hh
@@ -240,6 +240,8 @@
*/
virtual void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
+ virtual void squashDueToMemStall(DynInstPtr &inst, ThreadID tid);
+
/** Squash instructions from stage buffer */
virtual void squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid);
@@ -259,6 +261,13 @@
/** List of active thread ids */
std::list<ThreadID> *activeThreads;
+ /** Buffer of instructions switched out to mem-stall.
+ * Only used when using SwitchOnCacheMiss threading model
+ * Used as 1-to-1 mapping between ThreadID and Entry.
+ */
+ std::vector<DynInstPtr> switchedOutBuffer;
+ std::vector<bool> switchedOutValid;
+
/** Queue of all instructions coming from previous stage on this cycle. */
std::queue<DynInstPtr> insts[ThePipeline::MaxThreads];
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