[m5-dev] [PATCH 12 of 20] inorder: mem. mgmt. update

[Korey Sewell]

# HG changeset patch
# User Korey Sewell <ksew...@umich.edu>
# Date 1254427253 14400
# Node ID 3b3d9096f560c5e1c1c583cc7bcaf499165bd918
# Parent  8c8a99403944fd46bc964800f6c0d6ef0ef37e25
inorder: mem. mgmt. update
update address List and address Map to take
into account multiple threads

diff --git a/src/cpu/inorder/resources/cache_unit.cc 
b/src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -129,6 +129,8 @@
 int
 CacheUnit::getSlot(DynInstPtr inst)
 {
+    ThreadID tid = inst->readTid();
+    
     if (tlbBlocked[inst->threadNumber]) {
         return -1;
     }
@@ -140,7 +142,7 @@
     Addr req_addr = inst->getMemAddr();
 
     if (resName == "icache_port" ||
-        find(addrList.begin(), addrList.end(), req_addr) == addrList.end()) {
+        find(addrList[tid].begin(), addrList[tid].end(), req_addr) == 
addrList[tid].end()) {
 
         int new_slot = Resource::getSlot(inst);
 
@@ -148,8 +150,8 @@
             return -1;
 
         inst->memTime = curTick;
-        addrList.push_back(req_addr);
-        addrMap[req_addr] = inst->seqNum;
+        addrList[tid].push_back(req_addr);
+        addrMap[tid][req_addr] = inst->seqNum;
         DPRINTF(InOrderCachePort,
                 "[tid:%i]: [sn:%i]: Address %08p added to dependency list\n",
                 inst->readTid(), inst->seqNum, req_addr);
@@ -158,7 +160,7 @@
         DPRINTF(InOrderCachePort,
                 "[tid:%i] Denying request because there is an outstanding"
                 " request to/for addr. %08p. by [sn:%i] @ tick %i\n",
-                inst->readTid(), req_addr, addrMap[req_addr], inst->memTime);
+                inst->readTid(), req_addr, addrMap[tid][req_addr], 
inst->memTime);
         return -1;
     }
 }
@@ -166,15 +168,17 @@
 void
 CacheUnit::freeSlot(int slot_num)
 {
-    vector<Addr>::iterator vect_it = find(addrList.begin(), addrList.end(),
+    ThreadID tid = reqMap[slot_num]->inst->readTid();
+
+    vector<Addr>::iterator vect_it = find(addrList[tid].begin(), 
addrList[tid].end(),
             reqMap[slot_num]->inst->getMemAddr());
-    assert(vect_it != addrList.end());
+    assert(vect_it != addrList[tid].end());
 
     DPRINTF(InOrderCachePort,
             "[tid:%i]: Address %08p removed from dependency list\n",
             reqMap[slot_num]->inst->readTid(), (*vect_it));
 
-    addrList.erase(vect_it);
+    addrList[tid].erase(vect_it);
 
     Resource::freeSlot(slot_num);
 }
diff --git a/src/cpu/inorder/resources/cache_unit.hh 
b/src/cpu/inorder/resources/cache_unit.hh
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -198,9 +198,9 @@
 
     bool cacheBlocked;
 
-    std::vector<Addr> addrList;
+    std::vector<Addr> addrList[ThePipeline::MaxThreads];
 
-    std::map<Addr, InstSeqNum> addrMap;
+    std::map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
 
   public:
     int cacheBlkSize;
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